[RISCV] Fix registers class for esp32p4 HW loop instructions

espressif · Aug 29, 2024 · 8e1d87c · 8e1d87c
1 parent 8728786
commit 8e1d87c
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP4HWLP.td
@@ -41,7 +41,7 @@ def ESP_LP_SETUPI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm12:$count, uimm10_ste
   let Inst{0} = 1;
 }
 
-def ESP_LP_SETUP: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1, uimm13_step4:$offset),
+def ESP_LP_SETUP: Esp32P4Inst<(outs), (ins uimm1:$id, GPR:$rs1, uimm13_step4:$offset),
                    "esp.lp.setup\t $id, $rs1, $offset", []> 
 {
   bits<1> id;
@@ -145,7 +145,7 @@ def ESP_LP_COUNTI: Esp32P4Inst<(outs), (ins uimm1:$id, uimm12:$count),
   let Inst{0} = 1;
 }
 
-def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1),
+def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPR:$rs1),
                    "esp.lp.count\t $id, $rs1", []> 
 {
   bits<1> id;
@@ -156,7 +156,7 @@ def ESP_LP_COUNT: Esp32P4Inst<(outs), (ins uimm1:$id, GPRPIE:$rs1),
   let hasSideEffects = 1;
 
   let Inst{31-20} = 0xb000000000000;
-  let Inst{19-15} = 0xb00000;
+  let Inst{19-15} = rs1{4-0};
   let Inst{14} = 0;
   let Inst{13} = 1;
   let Inst{12} = 0;

diff --git a/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s b/llvm/test/MC/RISCV/esp32p4-hwlp-valid.s
@@ -9,7 +9,7 @@ dl_hwlp_test:
     esp.lp.counti 0, 4000
 # CHECK: esp.lp.counti	 0, 4000                # encoding: [0x2b,0x30,0x00,0xfa]
     esp.lp.count 0, a1
-# CHECK: esp.lp.count	 0, a1                  # encoding: [0x2b,0x20,0x00,0x00]
+# CHECK: esp.lp.count	 0, a1                  # encoding: [0x2b,0xa0,0x05,0x00]
     esp.lp.setupi 0, 1234, loop_last_instruction
 # CHECK: esp.lp.setupi	 0, 1234, loop_last_instruction # encoding: [0x2b'A',0x50'A',0x20'A',0x4d'A']
     # lp.setup 0, a1, loop_last_instruction