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Merge branch 'feature/esp32c61_lp_io_support' into 'master'
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feat(lp_io): Add LP_IO support for ESP32C61

Closes IDF-9317

See merge request espressif/esp-idf!33013
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@songruo
songruo committed Sep 11, 2024
2 parents 0b43a55 + 9994f49 commit 832e08c
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Showing 23 changed files with 600 additions and 117 deletions.
3 changes: 1 addition & 2 deletions components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -238,8 +238,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, C5: IO5) these pads' default configuration is low level
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5
// These pads' default configuration is low level

static void rtcio_deep_sleep_hold_test_first_stage(void)
{
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19 changes: 19 additions & 0 deletions components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
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Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_38, //GPIO38
GPIO_NUM_39, //GPIO39
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO25
#elif defined CONFIG_IDF_TARGET_ESP32S2
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
Expand Down Expand Up @@ -65,6 +66,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
#elif defined CONFIG_IDF_TARGET_ESP32S3
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
Expand Down Expand Up @@ -93,6 +95,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
Expand All @@ -107,6 +110,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
Expand All @@ -119,6 +123,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO12
#elif CONFIG_IDF_TARGET_ESP32P4
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
Expand All @@ -141,6 +146,20 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
};
#elif CONFIG_IDF_TARGET_ESP32C61
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 7
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 6 // IO6
#endif

#ifdef __cplusplus
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3 changes: 2 additions & 1 deletion components/esp_hw_support/include/esp_private/io_mux.h
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Expand Up @@ -37,7 +37,8 @@ typedef struct {
} rtc_io_status_t;

/**
* Enable/Disable LP_IO peripheral clock.
* @brief Enable/Disable LP_IO peripheral clock
*
* @param gpio_num GPIO number
* @param enable true to enable the clock / false to disable the clock
*/
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36 changes: 35 additions & 1 deletion components/esp_hw_support/port/esp32c61/io_mux.c
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Expand Up @@ -6,13 +6,23 @@

#include "freertos/FreeRTOS.h"
#include "esp_private/io_mux.h"
#include "esp_private/periph_ctrl.h"
#include "hal/gpio_ll.h"
#include "hal/rtc_io_ll.h"

//TODO: [ESP32C61] IDf-9316
#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()

static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)

#if CONFIG_ULP_COPROC_ENABLED
RTC_DATA_ATTR
#endif
static rtc_io_status_t s_rtc_io_status = {
.rtc_io_enabled_cnt = { 0 },
.rtc_io_using_mask = 0
};

esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
bool clk_conflict = false;
Expand All @@ -33,3 +43,27 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)

return ESP_OK;
}

void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_status.rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}
4 changes: 2 additions & 2 deletions components/hal/esp32c5/clk_tree_hal.c
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Expand Up @@ -73,10 +73,10 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)

void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
{
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
abort(); // TODO: IDF-10968
}

void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
{
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
abort(); // TODO: IDF-10968
}
13 changes: 0 additions & 13 deletions components/hal/esp32c5/include/hal/gpio_ll.h
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Original file line number Diff line number Diff line change
Expand Up @@ -488,19 +488,6 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
PIN_FUNC_SELECT(pin_name, func);
}

/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
__attribute__((always_inline))
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
}

/**
* @brief Select a function for the pin in the IOMUX
*
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13 changes: 0 additions & 13 deletions components/hal/esp32c61/include/hal/gpio_ll.h
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Original file line number Diff line number Diff line change
Expand Up @@ -486,19 +486,6 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
PIN_FUNC_SELECT(pin_name, func);
}

/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
__attribute__((always_inline))
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
}

/**
* @brief Select a function for the pin in the IOMUX
*
Expand Down
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