Add the PAC to the repo, add deprecation notice to README.md

Cargo.toml

@@ -1,35 +1,22 @@
 [package]
-name    = "esp8266-hal"
-version = "0.5.1"
-authors = [
-    "Robin Appelman <robin@icewind.nl>",
-    "Jesse Braham <jesse@beta7.io>",
-]
+name        = "esp8266-hal"
+version     = "0.5.1"
+authors     = ["Jesse Braham <jesse@beta7.io>", "Robin Appelman <robin@icewind.nl>"]
 edition     = "2021"
 description = "HAL for ESP8266 microcontrollers"
 repository  = "https://github.com/esp-rs/esp8266-hal"
 license     = "MIT OR Apache-2.0"
 
-keywords = [
-    "embedded",
-    "embedded-hal",
-    "esp",
-    "esp8266",
-    "no-std",
-]
-categories = [
-    "embedded",
-    "hardware-support",
-    "no-std",
-]
+keywords   = ["embedded", "embedded-hal", "esp", "esp8266", "no-std"]
+categories = ["embedded", "hardware-support", "no-std"]
 
 [dependencies]
 embedded-hal = { version = "0.2", features = ["unproven"] }
-esp8266      = "0.6"
+esp8266      = { version = "0.6", path = "./esp8266" }
 nb           = "1.0"
-paste        = { version = "1.0",  optional = true }
-void         = { version = "1.0",  default-features = false }
-xtensa-lx    = { version = "0.7",  features = ["esp8266"] }
+paste        = { version = "1.0", optional = true }
+void         = { version = "1.0", default-features = false }
+xtensa-lx    = { version = "0.7", features = ["esp8266"] }
 xtensa-lx-rt = { version = "0.12", features = ["esp8266"], optional = true }
 
 [dependencies.esp8266-hal-proc-macros]

README.md

@@ -1,6 +1,6 @@
 # esp8266-hal
 
-> ⚠️ **NOTE** this HAL is now in maintenence mode. No further development is planned at this time, however PRs may still be accepted.
+> ⚠️ **NOTE** this HAL is deprecated, no further development is planned.
 
 An experimental hardware abstraction layer for the [ESP8266](https://en.wikipedia.org/wiki/ESP8266) written in Rust.
 

esp8266/.cargo/config.toml

@@ -0,0 +1,5 @@
+[build]
+target = "xtensa-esp8266-none-elf"
+
+[unstable]
+build-std = ["core"]

esp8266/Cargo.toml

@@ -0,0 +1,38 @@
+[package]
+name = "esp8266"
+version = "0.7.0"
+edition = "2021"
+rust-version = "1.67"
+description = "Peripheral access crate for the ESP8266"
+repository = "https://github.com/esp-rs/esp-pacs"
+license = "MIT OR Apache-2.0"
+keywords = [
+    "embedded",
+    "esp8266",
+    "no-std",
+    "wifi",
+]
+categories = [
+    "embedded",
+    "hardware-support",
+    "no-std",
+]
+include = [
+    "src/**",
+    "build.rs",
+    "device.x",
+]
+
+[lib]
+bench = false
+test = false
+
+[dependencies]
+critical-section = { version = "1.1.1", optional = true }
+vcell = "0.1.3"
+xtensa-lx = "0.8.0"
+
+[features]
+default = ["xtensa-lx/esp8266"]
+rt = []
+impl-register-debug = []

esp8266/README.md

@@ -0,0 +1,30 @@
+# esp8266
+
+[![Crates.io](https://img.shields.io/crates/v/esp8266?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp8266)
+[![docs.rs](https://img.shields.io/docsrs/esp8266?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp8266)
+![Crates.io](https://img.shields.io/crates/l/esp8266?labelColor=1C2C2E&style=flat-square)
+[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
+
+A **P**eripheral **A**ccess **C**rate (**PAC**) for the **esp8266** from Espressif. See the [svd2rust] repository for more information on how to use this crate.
+
+If you find any problems with the included SVD file please open an issue in the [espressif/svd] repository so that the fixes can be applied upstream.
+
+[svd2rust]: https://github.com/rust-embedded/svd2rust
+[espressif/svd]: https://github.com/espressif/svd
+
+## [Documentation](https://docs.rs/esp8266)
+
+## License
+
+Licensed under either of:
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
+the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
+any additional terms or conditions.

esp8266/build.rs

@@ -0,0 +1,17 @@
+#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

esp8266/device.x

@@ -0,0 +1 @@
+

esp8266/src/dport.rs

@@ -0,0 +1,71 @@
+#[doc = r"Register block"]
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x04],
+    edge_int_enable: EDGE_INT_ENABLE,
+    _reserved1: [u8; 0x04],
+    spi_cache: SPI_CACHE,
+    _reserved2: [u8; 0x04],
+    dport_ctl: DPORT_CTL,
+    _reserved3: [u8; 0x08],
+    spi_interrupt_type: SPI_INTERRUPT_TYPE,
+    spi_cache_target: SPI_CACHE_TARGET,
+    ioswap: IOSWAP,
+}
+impl RegisterBlock {
+    #[doc = "0x04 - EDGE_INT_ENABLE"]
+    #[inline(always)]
+    pub const fn edge_int_enable(&self) -> &EDGE_INT_ENABLE {
+        &self.edge_int_enable
+    }
+    #[doc = "0x0c - Controls SPI memory-mapped caching"]
+    #[inline(always)]
+    pub const fn spi_cache(&self) -> &SPI_CACHE {
+        &self.spi_cache
+    }
+    #[doc = "0x14 - DPORT_CTL"]
+    #[inline(always)]
+    pub const fn dport_ctl(&self) -> &DPORT_CTL {
+        &self.dport_ctl
+    }
+    #[doc = "0x20 - SPI interrupt type register"]
+    #[inline(always)]
+    pub const fn spi_interrupt_type(&self) -> &SPI_INTERRUPT_TYPE {
+        &self.spi_interrupt_type
+    }
+    #[doc = "0x24 - Control where the cache is mapped (unconfirmed)"]
+    #[inline(always)]
+    pub const fn spi_cache_target(&self) -> &SPI_CACHE_TARGET {
+        &self.spi_cache_target
+    }
+    #[doc = "0x28 - IO Swap register"]
+    #[inline(always)]
+    pub const fn ioswap(&self) -> &IOSWAP {
+        &self.ioswap
+    }
+}
+#[doc = "EDGE_INT_ENABLE (rw) register accessor: EDGE_INT_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_int_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_int_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_int_enable`] module"]
+pub type EDGE_INT_ENABLE = crate::Reg<edge_int_enable::EDGE_INT_ENABLE_SPEC>;
+#[doc = "EDGE_INT_ENABLE"]
+pub mod edge_int_enable;
+#[doc = "DPORT_CTL (rw) register accessor: DPORT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dport_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dport_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dport_ctl`] module"]
+pub type DPORT_CTL = crate::Reg<dport_ctl::DPORT_CTL_SPEC>;
+#[doc = "DPORT_CTL"]
+pub mod dport_ctl;
+#[doc = "IOSWAP (rw) register accessor: IO Swap register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioswap::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioswap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioswap`] module"]
+pub type IOSWAP = crate::Reg<ioswap::IOSWAP_SPEC>;
+#[doc = "IO Swap register"]
+pub mod ioswap;
+#[doc = "SPI_CACHE (rw) register accessor: Controls SPI memory-mapped caching\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cache`] module"]
+pub type SPI_CACHE = crate::Reg<spi_cache::SPI_CACHE_SPEC>;
+#[doc = "Controls SPI memory-mapped caching"]
+pub mod spi_cache;
+#[doc = "SPI_INTERRUPT_TYPE (r) register accessor: SPI interrupt type register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_interrupt_type::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_interrupt_type`] module"]
+pub type SPI_INTERRUPT_TYPE = crate::Reg<spi_interrupt_type::SPI_INTERRUPT_TYPE_SPEC>;
+#[doc = "SPI interrupt type register"]
+pub mod spi_interrupt_type;
+#[doc = "SPI_CACHE_TARGET (rw) register accessor: Control where the cache is mapped (unconfirmed)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache_target::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache_target::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cache_target`] module"]
+pub type SPI_CACHE_TARGET = crate::Reg<spi_cache_target::SPI_CACHE_TARGET_SPEC>;
+#[doc = "Control where the cache is mapped (unconfirmed)"]
+pub mod spi_cache_target;

esp8266/src/dport/dport_ctl.rs

@@ -0,0 +1,66 @@
+#[doc = "Register `DPORT_CTL` reader"]
+pub type R = crate::R<DPORT_CTL_SPEC>;
+#[doc = "Register `DPORT_CTL` writer"]
+pub type W = crate::W<DPORT_CTL_SPEC>;
+#[doc = "Field `DPORT_CTL_DOUBLE_CLK` reader - "]
+pub type DPORT_CTL_DOUBLE_CLK_R = crate::BitReader;
+#[doc = "Field `DPORT_CTL_DOUBLE_CLK` writer - "]
+pub type DPORT_CTL_DOUBLE_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0"]
+    #[inline(always)]
+    pub fn dport_ctl_double_clk(&self) -> DPORT_CTL_DOUBLE_CLK_R {
+        DPORT_CTL_DOUBLE_CLK_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DPORT_CTL")
+            .field(
+                "dport_ctl_double_clk",
+                &format_args!("{}", self.dport_ctl_double_clk().bit()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<DPORT_CTL_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+impl W {
+    #[doc = "Bit 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dport_ctl_double_clk(&mut self) -> DPORT_CTL_DOUBLE_CLK_W<DPORT_CTL_SPEC> {
+        DPORT_CTL_DOUBLE_CLK_W::new(self, 0)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "DPORT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dport_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dport_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DPORT_CTL_SPEC;
+impl crate::RegisterSpec for DPORT_CTL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dport_ctl::R`](R) reader structure"]
+impl crate::Readable for DPORT_CTL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dport_ctl::W`](W) writer structure"]
+impl crate::Writable for DPORT_CTL_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets DPORT_CTL to value 0"]
+impl crate::Resettable for DPORT_CTL_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

esp8266/src/dport/edge_int_enable.rs

@@ -0,0 +1,101 @@
+#[doc = "Register `EDGE_INT_ENABLE` reader"]
+pub type R = crate::R<EDGE_INT_ENABLE_SPEC>;
+#[doc = "Register `EDGE_INT_ENABLE` writer"]
+pub type W = crate::W<EDGE_INT_ENABLE_SPEC>;
+#[doc = "Field `Register` reader - "]
+pub type REGISTER_R = crate::FieldReader<u32>;
+#[doc = "Field `Register` writer - "]
+pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+#[doc = "Field `wdt_edge_int_enable` reader - Enable the watchdog timer edge interrupt"]
+pub type WDT_EDGE_INT_ENABLE_R = crate::BitReader;
+#[doc = "Field `wdt_edge_int_enable` writer - Enable the watchdog timer edge interrupt"]
+pub type WDT_EDGE_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `timer1_edge_int_enable` reader - Enable the timer1 edge interrupt"]
+pub type TIMER1_EDGE_INT_ENABLE_R = crate::BitReader;
+#[doc = "Field `timer1_edge_int_enable` writer - Enable the timer1 edge interrupt"]
+pub type TIMER1_EDGE_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:31"]
+    #[inline(always)]
+    pub fn register(&self) -> REGISTER_R {
+        REGISTER_R::new(self.bits)
+    }
+    #[doc = "Bit 0 - Enable the watchdog timer edge interrupt"]
+    #[inline(always)]
+    pub fn wdt_edge_int_enable(&self) -> WDT_EDGE_INT_ENABLE_R {
+        WDT_EDGE_INT_ENABLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable the timer1 edge interrupt"]
+    #[inline(always)]
+    pub fn timer1_edge_int_enable(&self) -> TIMER1_EDGE_INT_ENABLE_R {
+        TIMER1_EDGE_INT_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EDGE_INT_ENABLE")
+            .field("register", &format_args!("{}", self.register().bits()))
+            .field(
+                "wdt_edge_int_enable",
+                &format_args!("{}", self.wdt_edge_int_enable().bit()),
+            )
+            .field(
+                "timer1_edge_int_enable",
+                &format_args!("{}", self.timer1_edge_int_enable().bit()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<EDGE_INT_ENABLE_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31"]
+    #[inline(always)]
+    #[must_use]
+    pub fn register(&mut self) -> REGISTER_W<EDGE_INT_ENABLE_SPEC> {
+        REGISTER_W::new(self, 0)
+    }
+    #[doc = "Bit 0 - Enable the watchdog timer edge interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn wdt_edge_int_enable(&mut self) -> WDT_EDGE_INT_ENABLE_W<EDGE_INT_ENABLE_SPEC> {
+        WDT_EDGE_INT_ENABLE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Enable the timer1 edge interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn timer1_edge_int_enable(&mut self) -> TIMER1_EDGE_INT_ENABLE_W<EDGE_INT_ENABLE_SPEC> {
+        TIMER1_EDGE_INT_ENABLE_W::new(self, 1)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "EDGE_INT_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_int_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_int_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EDGE_INT_ENABLE_SPEC;
+impl crate::RegisterSpec for EDGE_INT_ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`edge_int_enable::R`](R) reader structure"]
+impl crate::Readable for EDGE_INT_ENABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`edge_int_enable::W`](W) writer structure"]
+impl crate::Writable for EDGE_INT_ENABLE_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets EDGE_INT_ENABLE to value 0"]
+impl crate::Resettable for EDGE_INT_ENABLE_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}