Optimized register sizes & continued development of DMA HALs

hw/ip/dma/data/dma.hjson

@@ -38,27 +38,19 @@
       swaccess: "rw",
       hwaccess: "hro",
       hwqe:     "true", // enable `qe` latched signal of software write pulse
+      // Dimensioned to 16 bits to allow for 64kB transfers on 1D
       fields: [
-        { bits: "31:0", name: "SIZE", desc: "DMA counter D1 and start" }
+        { bits: "15:0", name: "SIZE", desc: "DMA counter D1 and start" }
       ]
     },
     { name:     "SIZE_TR_D2",
       desc:     "Number of bytes to copy from, defined with respect to the second dimension",
       swaccess: "rw",
       hwaccess: "hro",
       hwqe:     "true", // enable `qe` latched signal of software write pulse
+      // Dimensioned to 16 bits to allow for 64kB transfers on 2D
       fields: [
-        { bits: "31:0", name: "SIZE", desc: "DMA counter D2" }
-      ]
-    },
-    { name:     "SIZE_IN",
-      desc:     "Dimensions of the input matrix",
-      swaccess: "rw",
-      hwaccess: "hro",
-      hwqe:     "true", // enable `qe` latched signal of software write pulse
-      fields: [
-        { bits: "15:0", name: "D1", desc: "Size of dimension 1" },
-        { bits: "31:16", name: "D2", desc: "Size of dimension 2" }
+        { bits: "15:0", name: "SIZE", desc: "DMA counter D2" }
       ]
     },
     { name:     "STATUS",
@@ -77,13 +69,15 @@
       desc:     "Increment number of src/dst pointer every time a word is copied",
       swaccess: "rw",
       hwaccess: "hro",
+      // Dimensioned to allow a maximum of 64 byte stride (a stride of 15 places for a data_type_word case) 
+      // for the 1D case and 64kB stride for the 2D case (a stride of 15 places for a data_type_word case)
       fields: [
-        { bits: "7:0", 
+        { bits: "5:0", 
           name: "SRC_PTR_INC_D1", 
           desc: "Source pointer d1 increment",
           resval:4
         },
-        { bits: "23:8", 
+        { bits: "28:6", 
           name: "SRC_PTR_INC_D2", 
           desc: "Source pointer d2 increment",
           resval:4
@@ -95,12 +89,12 @@
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "7:0", 
+        { bits: "5:0", 
           name: "DST_PTR_INC_D1", 
           desc: "Destination pointer increment",
           resval:4
         },
-        { bits: "23:8", 
+        { bits: "28:6", 
           name: "DST_PTR_INC_D2", 
           desc: "Address pointer increment",
           resval:4
@@ -171,10 +165,10 @@
       hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
       resval:   0,
       fields: [
-        { bits: "7:0", name: "LEFT_PAD", desc: "Left margin padding (1D/2D)"},
-        { bits: "15:8", name: "RIGHT_PAD", desc: "Right margin padding (1D/2D)"},
-        { bits: "23:16", name: "TOP_PAD", desc: "Top margin padding (2D)"},
-        { bits: "31:24", name: "BOTTOM_PAD", desc: "Bottom margin padding (2D)"}
+        { bits: "5:0", name: "LEFT_PAD", desc: "Left margin padding (1D/2D)"},
+        { bits: "11:6", name: "RIGHT_PAD", desc: "Right margin padding (1D/2D)"},
+        { bits: "17:12", name: "TOP_PAD", desc: "Top margin padding (2D)"},
+        { bits: "22:17", name: "BOTTOM_PAD", desc: "Bottom margin padding (2D)"}
       ]
     },
     { name:    "WINDOW_SIZE",
@@ -183,7 +177,7 @@
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "31:0", name: "WINDOW_SIZE", desc: ""}
+        { bits: "12:0", name: "WINDOW_SIZE", desc: ""}
       ]
     },
     { name:    "WINDOW_COUNT",
@@ -194,7 +188,7 @@
       hwaccess: "hrw",
       resval: 0,
       fields: [
-        { bits: "31:0", name: "WINDOW_COUNT", desc: "Number of windows transferred in the transaction" }
+        { bits: "7:0", name: "WINDOW_COUNT", desc: "Number of windows transferred in the transaction" }
       ]
     },
     { name:    "INTERRUPT_EN",

hw/ip/dma/rtl/dma_reg_pkg.sv

@@ -7,7 +7,7 @@
 package dma_reg_pkg;
 
   // Address widths within the block
-  parameter int BlockAw = 7;
+  parameter int BlockAw = 6;
 
   ////////////////////////////
   // Typedefs for registers //
@@ -20,26 +20,15 @@ package dma_reg_pkg;
   typedef struct packed {logic [31:0] q;} dma_reg2hw_addr_ptr_reg_t;
 
   typedef struct packed {
-    logic [31:0] q;
+    logic [15:0] q;
     logic        qe;
   } dma_reg2hw_size_tr_d1_reg_t;
 
   typedef struct packed {
-    logic [31:0] q;
+    logic [15:0] q;
     logic        qe;
   } dma_reg2hw_size_tr_d2_reg_t;
 
-  typedef struct packed {
-    struct packed {
-      logic [15:0] q;
-      logic        qe;
-    } d1;
-    struct packed {
-      logic [15:0] q;
-      logic        qe;
-    } d2;
-  } dma_reg2hw_size_in_reg_t;
-
   typedef struct packed {
     struct packed {
       logic q;
@@ -52,13 +41,13 @@ package dma_reg_pkg;
   } dma_reg2hw_status_reg_t;
 
   typedef struct packed {
-    struct packed {logic [7:0] q;} src_ptr_inc_d1;
-    struct packed {logic [15:0] q;} src_ptr_inc_d2;
+    struct packed {logic [5:0] q;} src_ptr_inc_d1;
+    struct packed {logic [22:0] q;} src_ptr_inc_d2;
   } dma_reg2hw_src_ptr_inc_reg_t;
 
   typedef struct packed {
-    struct packed {logic [7:0] q;} dst_ptr_inc_d1;
-    struct packed {logic [15:0] q;} dst_ptr_inc_d2;
+    struct packed {logic [5:0] q;} dst_ptr_inc_d1;
+    struct packed {logic [22:0] q;} dst_ptr_inc_d2;
   } dma_reg2hw_dst_ptr_inc_reg_t;
 
   typedef struct packed {
@@ -73,15 +62,27 @@ package dma_reg_pkg;
   typedef struct packed {logic q;} dma_reg2hw_dim_config_reg_t;
 
   typedef struct packed {
-    struct packed {logic [7:0] q;} left_pad;
-    struct packed {logic [7:0] q;} right_pad;
-    struct packed {logic [7:0] q;} top_pad;
-    struct packed {logic [7:0] q;} bottom_pad;
+    struct packed {
+      logic [5:0] q;
+      logic       qe;
+    } left_pad;
+    struct packed {
+      logic [5:0] q;
+      logic       qe;
+    } right_pad;
+    struct packed {
+      logic [5:0] q;
+      logic       qe;
+    } top_pad;
+    struct packed {
+      logic [5:0] q;
+      logic       qe;
+    } bottom_pad;
   } dma_reg2hw_pad_reg_t;
 
-  typedef struct packed {logic [31:0] q;} dma_reg2hw_window_size_reg_t;
+  typedef struct packed {logic [12:0] q;} dma_reg2hw_window_size_reg_t;
 
-  typedef struct packed {logic [31:0] q;} dma_reg2hw_window_count_reg_t;
+  typedef struct packed {logic [7:0] q;} dma_reg2hw_window_count_reg_t;
 
   typedef struct packed {
     struct packed {logic q;} transaction_done;
@@ -94,55 +95,53 @@ package dma_reg_pkg;
   } dma_hw2reg_status_reg_t;
 
   typedef struct packed {
-    logic [31:0] d;
-    logic        de;
+    logic [7:0] d;
+    logic       de;
   } dma_hw2reg_window_count_reg_t;
 
   // Register -> HW type
   typedef struct packed {
-    dma_reg2hw_src_ptr_reg_t src_ptr;  // [382:351]
-    dma_reg2hw_dst_ptr_reg_t dst_ptr;  // [350:319]
-    dma_reg2hw_addr_ptr_reg_t addr_ptr;  // [318:287]
-    dma_reg2hw_size_tr_d1_reg_t size_tr_d1;  // [286:254]
-    dma_reg2hw_size_tr_d2_reg_t size_tr_d2;  // [253:221]
-    dma_reg2hw_size_in_reg_t size_in;  // [220:187]
-    dma_reg2hw_status_reg_t status;  // [186:183]
-    dma_reg2hw_src_ptr_inc_reg_t src_ptr_inc;  // [182:159]
-    dma_reg2hw_dst_ptr_inc_reg_t dst_ptr_inc;  // [158:135]
-    dma_reg2hw_slot_reg_t slot;  // [134:103]
-    dma_reg2hw_data_type_reg_t data_type;  // [102:101]
-    dma_reg2hw_mode_reg_t mode;  // [100:99]
-    dma_reg2hw_dim_config_reg_t dim_config;  // [98:98]
-    dma_reg2hw_pad_reg_t pad;  // [97:66]
-    dma_reg2hw_window_size_reg_t window_size;  // [65:34]
-    dma_reg2hw_window_count_reg_t window_count;  // [33:2]
+    dma_reg2hw_src_ptr_reg_t src_ptr;  // [279:248]
+    dma_reg2hw_dst_ptr_reg_t dst_ptr;  // [247:216]
+    dma_reg2hw_addr_ptr_reg_t addr_ptr;  // [215:184]
+    dma_reg2hw_size_tr_d1_reg_t size_tr_d1;  // [183:167]
+    dma_reg2hw_size_tr_d2_reg_t size_tr_d2;  // [166:150]
+    dma_reg2hw_status_reg_t status;  // [149:146]
+    dma_reg2hw_src_ptr_inc_reg_t src_ptr_inc;  // [145:117]
+    dma_reg2hw_dst_ptr_inc_reg_t dst_ptr_inc;  // [116:88]
+    dma_reg2hw_slot_reg_t slot;  // [87:56]
+    dma_reg2hw_data_type_reg_t data_type;  // [55:54]
+    dma_reg2hw_mode_reg_t mode;  // [53:52]
+    dma_reg2hw_dim_config_reg_t dim_config;  // [51:51]
+    dma_reg2hw_pad_reg_t pad;  // [50:23]
+    dma_reg2hw_window_size_reg_t window_size;  // [22:10]
+    dma_reg2hw_window_count_reg_t window_count;  // [9:2]
     dma_reg2hw_interrupt_en_reg_t interrupt_en;  // [1:0]
   } dma_reg2hw_t;
 
   // HW -> register type
   typedef struct packed {
-    dma_hw2reg_status_reg_t status;  // [34:33]
-    dma_hw2reg_window_count_reg_t window_count;  // [32:0]
+    dma_hw2reg_status_reg_t status;  // [10:9]
+    dma_hw2reg_window_count_reg_t window_count;  // [8:0]
   } dma_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 7'h0;
-  parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 7'h4;
-  parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 7'h8;
-  parameter logic [BlockAw-1:0] DMA_SIZE_TR_D1_OFFSET = 7'hc;
-  parameter logic [BlockAw-1:0] DMA_SIZE_TR_D2_OFFSET = 7'h10;
-  parameter logic [BlockAw-1:0] DMA_SIZE_IN_OFFSET = 7'h14;
-  parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 7'h18;
-  parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_OFFSET = 7'h1c;
-  parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_OFFSET = 7'h20;
-  parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 7'h24;
-  parameter logic [BlockAw-1:0] DMA_DATA_TYPE_OFFSET = 7'h28;
-  parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 7'h2c;
-  parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 7'h30;
-  parameter logic [BlockAw-1:0] DMA_PAD_OFFSET = 7'h34;
-  parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 7'h38;
-  parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 7'h3c;
-  parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 7'h40;
+  parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 6'h0;
+  parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 6'h4;
+  parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 6'h8;
+  parameter logic [BlockAw-1:0] DMA_SIZE_TR_D1_OFFSET = 6'hc;
+  parameter logic [BlockAw-1:0] DMA_SIZE_TR_D2_OFFSET = 6'h10;
+  parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 6'h14;
+  parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_OFFSET = 6'h18;
+  parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_OFFSET = 6'h1c;
+  parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 6'h20;
+  parameter logic [BlockAw-1:0] DMA_DATA_TYPE_OFFSET = 6'h24;
+  parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 6'h28;
+  parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 6'h2c;
+  parameter logic [BlockAw-1:0] DMA_PAD_OFFSET = 6'h30;
+  parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 6'h34;
+  parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 6'h38;
+  parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 6'h3c;
 
   // Reset values for hwext registers and their fields
   parameter logic [1:0] DMA_STATUS_RESVAL = 2'h1;
@@ -156,7 +155,6 @@ package dma_reg_pkg;
     DMA_ADDR_PTR,
     DMA_SIZE_TR_D1,
     DMA_SIZE_TR_D2,
-    DMA_SIZE_IN,
     DMA_STATUS,
     DMA_SRC_PTR_INC,
     DMA_DST_PTR_INC,
@@ -171,24 +169,23 @@ package dma_reg_pkg;
   } dma_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] DMA_PERMIT[17] = '{
+  parameter logic [3:0] DMA_PERMIT[16] = '{
       4'b1111,  // index[ 0] DMA_SRC_PTR
       4'b1111,  // index[ 1] DMA_DST_PTR
       4'b1111,  // index[ 2] DMA_ADDR_PTR
-      4'b1111,  // index[ 3] DMA_SIZE_TR_D1
-      4'b1111,  // index[ 4] DMA_SIZE_TR_D2
-      4'b1111,  // index[ 5] DMA_SIZE_IN
-      4'b0001,  // index[ 6] DMA_STATUS
-      4'b0111,  // index[ 7] DMA_SRC_PTR_INC
-      4'b0111,  // index[ 8] DMA_DST_PTR_INC
-      4'b1111,  // index[ 9] DMA_SLOT
-      4'b0001,  // index[10] DMA_DATA_TYPE
-      4'b0001,  // index[11] DMA_MODE
-      4'b0001,  // index[12] DMA_DIM_CONFIG
-      4'b1111,  // index[13] DMA_PAD
-      4'b1111,  // index[14] DMA_WINDOW_SIZE
-      4'b1111,  // index[15] DMA_WINDOW_COUNT
-      4'b0001  // index[16] DMA_INTERRUPT_EN
+      4'b0011,  // index[ 3] DMA_SIZE_TR_D1
+      4'b0011,  // index[ 4] DMA_SIZE_TR_D2
+      4'b0001,  // index[ 5] DMA_STATUS
+      4'b1111,  // index[ 6] DMA_SRC_PTR_INC
+      4'b1111,  // index[ 7] DMA_DST_PTR_INC
+      4'b1111,  // index[ 8] DMA_SLOT
+      4'b0001,  // index[ 9] DMA_DATA_TYPE
+      4'b0001,  // index[10] DMA_MODE
+      4'b0001,  // index[11] DMA_DIM_CONFIG
+      4'b0111,  // index[12] DMA_PAD
+      4'b0011,  // index[13] DMA_WINDOW_SIZE
+      4'b0001,  // index[14] DMA_WINDOW_COUNT
+      4'b0001  // index[15] DMA_INTERRUPT_EN
   };
 
 endpackage