Update chapter-06 exercise 6

solutions/chapter-02.md

@@ -124,7 +124,7 @@
 	3. 0111 + 0001
 		1. Yes because result should be 0 1000 which is 8 but without 5th byte result will be 1000 which is -8.
 	4. 1000 − 0001
-		1. No.
+		1. Yes because 1000 is '-8', 0001 is '1', the result should be -8 - 1 = -9. To subtract '1' we should represent it as negative '1111' and add to '1000' (-8). 1000 + 1111 = 1 0111 (-9). But without first (5's) bit the answer is positive 7 (0111). So, overflow occurred.
 	5. 0111 + 1001
 		1.  No.
 ---
@@ -140,7 +140,7 @@
 	1. If the two unsigned number added and leftmost digit of the sum will be 1 this means an overflow occured. Because unsigned numbers are positive and leftmost digit is 0.
 ---
 24. Create two 16-bit unsigned integers such that their sum causes an overflow.
-	1. 0111 1111 1111 1111 + 0000 0000 0000 0001
+	1. 1111 1111 1111 1111 + 0000 0000 0000 0001
 ---
 25. Why does the sum of a negative 2’s complement number and a positive 2’s complement number never generate an overflow?
 	1. When adding a negative and a positive 2's complement number, overflow is not possible because the result will always be within the range of representable values for the given bit width.

solutions/chapter-03.md

@@ -38,7 +38,7 @@
 	3. 0 1   1 0 0
 	4. 1 0   0 1 0
 	5. 1 1   0 0 1
-    Z in terms of A and B is output of logical function AND
+    Z in terms of A and B is output of logical function AND.
 ---
 7. There is ambiguity at output when A = 1 and B = 1. Output voltage is threshold voltage, so it's keep switching.
 ---
@@ -121,7 +121,7 @@
 ---
 26. [falstad link | Live Circuit](https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgDOB0YzCsICMZICYaoOyYMxgByoBsAnCZiHBAlZQKYC0iiAUAGYgAsRnI6+lVAP6UkkBCjCoWAd0HDUvOEL5wi4FgCV5SFcoH4IRrtXBmUcdlx59MqHVnsJE4qFNkP8A-SDy8wHj5+OjjoGhzcvDg46kExXGIS0NIcMQLR6pyhvvG8Lknucln2wcW+YQFF2cFBYP4sAOZc1crNJfj+Gk1BrUEd5h6RtvZDGRpyaXwEvkTp8ZUzwtNDIgsQRHYgNhv2ARwM24pmREfOrpIpIAe8dsa3Cflu0nLrnMY748ebEJh14Vc2TD9H79PLnZIeH7zECYWZdMyGYz4bJGDzXLZHdH3PZXRBEdaYkjqE5KRJPNFEyiwq6U-ECBYMSlwanUFmQqnqdbTALaRmxalMfEc8wmUTGCxovEE3iCkH1OSymH9LHAinEt404nfNVbb663YsACyAL1ByOxlQ4jRyPsgquiNxnOt2QYLptjs+DC8EFdtvdvs97p9DtRCvdnAEXpRgcMXEj4fp1pgSE4ModeJjEEQqftyez8txBAEUppJHsJYZyC8WxlVeLQsrRZrhY1Nkb1YjherbclTb5pdtlPbkYzTD7Q971btjLLHuHca7I6dCuYuRHTc7leQeRUM-LKi3fxdzD+iAPku35QHV8PtfUTEvKIvfyYu+3PrPiZXl4YnYfL8-T0TxlP8yFtTdnzvXEfwg794mnYC5xYABJFtXmvNsoBoFC0NxXcwLw+ksMoFhEFaL1kx9D5jBwMxLDIn0CPze1Y2YiBdhIhjrz-b0F3YujSNoPcrjdWMA14Dj6KEgiHz9MTmA4pwSIAGWgtc8IzTckBANgAEMABsAGc6DFFhVIfeDRzPKzOTMPSjJMiRGl0ARcHUQDYSInkXK2aZALUcVRQkcwrTkbZNkBCoPEOXhwoNORAI+Dy-gWRKNUS7UOEirMVHuMECkuGKfJJURHguKw3NUdQHVQNRSvBdwOEqnBWgdFqRjJcq5BqzY2pSjw+t4Nr5g8SravUZr+rkSabnidqNGNQaQHwGxgnYq1tBqjV01nYwNWCowrSaNq4QdN5xWizZghm-5VtPFQak6iEst4c6fLe-LyQSh6wkA+bUoe1o-tVMKoj+VbWgWCH7BsN7vMAoRixURRAv2kUJSaQDOAzLGtIZSl-t8SGdVCRj1H+yUhSGdEhkrIVgkVWmtE1KrHXYuq9tMcVQrMcbeerfH1D59nlxZvn+0R-5FQZgm-jOAq0TumVYco5yIAjYw4DPAYXi4DN1Yg-ZYcwoZPq6sxCZwEGLYqImDSN17KJMdWnsagEwc6R6yohXX5uhz1squERsUpuUg+mIECxp5MGBEOHQ+sGU457FchWY2O-JzBkbDEkRYzWK9Vvt925w9eXyQd5akRd73CnRm92WjHtK7YlNXtd54zCHHyAiaLMGyQXaA6g9F86sRVp0pO1y-N-t0Tnp8FSnzD0QL1eRINXll7vKjOnVrmQssVOP3vEs2IT9ObHPpfbP7ReWejJ9MZUSlAMA1FtEAgMv-zsw0e5o+zZsg51DM2O0RdPh-X3AIFOPcfJPhelXHysYzbPTATjN8sQO4JwniIRU2ck6Yjwagc07JY4RSTplEuvpjA0PqgrSusdzRByOKguuPo1pB21LrchHFY4ahxPPCsbMHgNU7j6VYuI2R91xFnaCHECEb13iw+o+wSx0IXmEGePsWaujhAvEaN8RJwg4SYshkwOEjS3veSYE8LF-wPodQBdiwgTwrDg9RNh8E6ldC+KejhPT+NNAE3uPkM5IxHCyDQn9dxjC-lbPeQV0ZWmNF-AJiBZy8N5jzLxATcmkNBkosBISPBpM2GkgRpTYn3UjCUxBTCdy1NYdg+ppMwltO0W7V0a4JGbA1vQiuIl4jMnvAEkZoiFYKgCZwIJThzxTM2D4LJAVPRjH6d02I8yhmbMjGMcZ3ksnU2mfrBxYpD7OWWZkvJzCGRvSWXsrZyzdwiB8AyF5zzljN22UgAU6TqSdMuBs4YXD7DTOwQs8sVzNgkKjgEmFILWYMjiQKMY8KkXxHhUCkpvJ0lCiyQpEU-9zlNCyZLLJbTQG-mTJi1FBSrhvWnGMO0oTDm1N6hdHFmwKIItfF5JJAC0RMtHGMe+QL55CtFlk6cuLPQBN-Gy20+tx4ittAE7IbDAVMtyVymwAK0QMoZkytaFy5Uox5ZIg5crbFyuxrZfeZynGCvgoa+CwsnU2PIkaqaPKGamu4T611XLjX7CZeLU1dUNXKudeRK1vRwUIsxSINFaIRDpyTXSqVo48FKqmdMaV0wx4QpEi+PBxrc27JLXm5N5aRFUpPpSuOMcPqqxrfcOtMIoqtuVG9SOGhzIzKFlOFZktjD2WMqZftBN4IrLGFmHSBlx1OQVAOvgU4VgC31TYMl1Mc30q8aOBlu7fz7vvNTMte6ZQMwNd649Ek10q0pabJtyZ47LofRejtj7A7tpDsuqdp7Oyzv1YB+CqZvCPLAzodtrzgPgcjJB3ttzOy9p-dbX8IGAMKCjpBzFb1q30s7Lhv87jl3EbxYehsVghjMR8DR+NtGhS0d2lYGd8QSprOwU0djrR2PAk+LUWKRxz3sfBkJztGIPb6l8N61jsQqa7pWba3woJd0JL1uTfo19lN5BzNRrOgwt1XQxf6yYIhUXcg8Gp5icT9PfRgUZrU8UciOec8CgG6RWjBAphMI8nm-irEs-56Y5mvzwJKHNJzKrXPnyAA)
 	1. Solution:
-![Solution](_attachments/image.png)
+![Solution](https://github.com/user-attachments/assets/88e23e99-0349-474e-b9c9-910be4a35cc0)
 ---
 27. 14 bit address can store 2^14 byte. If the nibble takes half the space of the byte, this memory can store 2^14 * 2 = 2^15 nibbles.
 ---

solutions/chapter-06.md

@@ -58,58 +58,64 @@
 5. 88 * 3. Because it needs less operation count.
 ---
 6. Solution:
-	1. First
-		1. Start
-		2. Operation
-			1. Multiply two numbers
-		3. Stop
-	2. Second
-		1. Start
-		2. Initialize
-		3. Operation
-			1. Find smaller number
-			2. Sum result with bigger number
-			3. Decrement smaller number by 1
-			4. If smaller number bigger than 0 return to instruction 2 before.
-			5. Else you found the result
-		4. Stop
-	3. Third
-		1. Start
-		2. Initialize
-			1. LDI R1 SEC_NUM
-			2. LDI R2 FRS_NUM
-			3. AND R0 R0 #0
-			4. AND R4 R4 #0
-			5. AND R5 R5 #0 (SMALL_NUM)
-			6. AND R6 R6 #0 (BIG_NUM)
-			7. AND R7 R7 #0 (RESULT)
-		3. Operation
-			1. NOT R4 R2
-			2. ADD R4 R4 #1
-			3. ADD R5 R1 R4
-			4. BRn #7
-			5. BRp #3
-			6. ADD R6 R2 #0
-			7. ADD R5 R1 #0
-			8. BRnzp DETERMINE_IF_SMALLER_POSITIVE
-			9. ADD R6 R1 #0
-			10. ADD R5 R2 #0
-			11. BRnzp DETERMINE_IF_SMALLER_POSITIVE
-			12. ADD R6 R2 #0
-			13. ADD R5 R1 #0
-			14. [DETERMINE_IF_SMALLER_POSITIVE] BRn SMALLER_NEGATIVE_LOOP_START
-			15. BRp SMALLER_POSITIVE_LOOP_START
-			16. BRnzp RESULT (this means if smaller not positive or negative, so smaller is zero so the result is too.)
-			17. [SMALLER_NEGATIVE_LOOP_START] ADD R7 R6 #0
-			18. ADD R5 R5 #1 (increment negative smaller number)
-			19. BRn [SMALLER_NEGATIVE_LOOP_START]
-			20. BRnzp RESULT
-			21. [SMALLER_POSITIVE_LOOP_START] ADD R7 R6 #0
-			22. ADD R5 R5 #-1 (decrement positive smaller number)
-			23. BRp [SMALLER_POSITIVE_LOOP_START]
-			24. BRnzp [RESULT]
-			25. [RESULT] (Result is R7)
-		4. Exit
+	1. Flowchart:
+![Solution](_attachments/6.6%20multiplication.png)
+	2. Assembler code in image:
+![Solution](_attachments/6.6.%20asm%20code.png)
+	3. Actual assembler code:
+		AND R3, R3, #0
+     		ADD R6, R0, #0
+		ADD R7, R1, #0
+		AND R4, R7, #-1
+       		BRz DONE
+      		AND R4, R6, #-1
+		BRz DONE
+       		BRn NEG1
+       		AND R4, R7, #-1
+       		BRp POS2
+      		NOT R7, R7
+       		ADD R7, R7, #1
+      		BRnzp NMULT
+	NEG1    NOT R6, R6
+     		ADD R6, R6, #1
+       		AND R4, R7, #-1
+      		BRn POS1
+	NMULT   NOT R2, R6
+      		ADD R2, R2, #1
+       		ADD R4, R7, R2
+      		BRn COUNT1
+		ADD R5, R6, #0
+	LOOP1   ADD R3, R3, R7
+     		ADD R5, R5, #-1
+      		BRp LOOP1
+      		NOT R3, R3
+      		ADD R3, R3, #1
+       		BRnzp DONE
+	COUNT1  ADD R5, R7, #0
+	LOOP2   ADD R3, R3, R6
+      		ADD R5, R5, #-1
+      		BRp LOOP2
+		NOT R3, R3
+      		ADD R3, R3, #1
+		BRnzp DONE
+	POS1    NOT R7, R7
+      		ADD R7, R7, #1
+	POS2    NOT R2, R6
+      		ADD R2, R2, #1
+      		ADD R4, R7, R2
+      		BRn COUNT2
+      		ADD R5, R6, #0
+	LOOP3   ADD R3, R3, R7
+      		ADD R5, R5, #-1
+      		BRp LOOP3
+      		BRnzp DONE
+	COUNT2  ADD R5, R7, #0
+	LOOP4   ADD R3, R3, R6
+      		ADD R5, R5, #-1
+      		BRp LOOP4
+     		BRnzp DONE
+	DONE    TRAP x25
+    .END
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 7. It sums correspending elements of specific lengthed two list (i guess) and store them.
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