Add GenericTAP and enable JTAGBone access via jtagremote in litex_sim

[cklarhorst]

This PR introduces a minimal, vendor-agnostic JTAG TAP implementation (GenericTAP) that works both in simulation and on regular FPGAs.

Note: This is intentionally a minimal TAP (not full IEEE 1149.1 compliance: no boundary scan / EXTEST / SAMPLE / PRELOAD).
Tested: It was tested in litex_sim and on a basys3 board

When to use?

• When you need JTAG on non-dedicated FPGA I/O pins
• When you want to debug low-level JTAG signaling in simulation, especially around JTAGBone

How to test in litex_sim:

create test.cfg:

interface remote_bitbang
remote_bitbang_host localhost
remote_bitbang_port 44853
set _CHIPNAME auto0

run:

litex_sim --with-jtagbone
litex_server --jtag-config test.cfg  --jtag
litex_cli --regs
0xf0000000 : 0x00000000 ctrl_reset
0xf0000004 : 0x12345678 ctrl_scratch
0xf0000008 : 0x00000000 ctrl_bus_errors
0xf0001000 : 0x0003d090 timer0_load
0xf0001004 : 0x00000000 timer0_reload
0xf0001008 : 0x00000001 timer0_en
0xf000100c : 0x00000001 timer0_update_value
0xf0001010 : 0x00000000 timer0_value

Be aware it is very slow in the simulator
Because the chunk size in openocd is way to large for the simulator:

diff --git a/litex/build/openocd.py b/litex/build/openocd.py
index 62644da5f..59015b08e 100644
--- a/litex/build/openocd.py
+++ b/litex/build/openocd.py
@@ -153,7 +153,7 @@ proc jtagstream_drain {tap tx chunk_rx max_rx} {
 proc jtagstream_rxtx {tap client is_poll} {
     if {![$client eof]} {
         set tx [$client read 16]
-        set rx [jtagstream_drain $tap $tx 128 4096]
+        set rx [jtagstream_drain $tap $tx 16 64]
         if {[string length $rx]} {
             #echo [string length $rx]
             $client puts -nonewline $rx

Because the default jtagremote has:

--- a/litex/build/sim/core/modules/jtagremote/jtagremote.c
+++ b/litex/build/sim/core/modules/jtagremote/jtagremote.c
@@ -222,8 +222,8 @@ static int jtagremote_tick(void *sess, uint64_t time_ps)
   }

   s->cntticks++;
-  if(s->cntticks % 10)
-         return RC_OK;
+  //if(s->cntticks % 10)
+       //  return RC_OK;

   if(s->datalen)

Real world (e.g. Basys3):

board target file:

from litex.soc.cores import uart
from litex.soc.cores.jtag import JTAGPHY, GenericTAP
name = "test"
self.jtag_tap = GenericTAP(platform.request("jtag"))
jtagbone_phy = JTAGPHY(device=self.platform.device, chain=0x1, platform=self.platform, jtag=self.jtag_tap)
jtagbone = uart.UARTBone(
    phy           = jtagbone_phy,
    clk_freq      = self.sys_clk_freq,
    address_width = self.bus.address_width
)
self.add_module(name=name,          module=jtagbone)
self.bus.add_master(name=name, master=jtagbone.wishbone)

openocd output:

openocd  --file test.cfg
Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
jtag
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : J-Link ARM Lite V8 compiled Mar 14 2018 16:03:26
Info : Hardware version: 8.00
Info : VTarget = 3.410 V
Info : clock speed 1000 kHz
Warn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!
Info : JTAG tap: auto0.tap tap/device found: 0x1c0de001 (mfg: 0x000 (<invalid>), part: 0xc0de, ver: 0x1)
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 4 -expected-id 0x1c0de001"
Warn : gdb services need one or more targets defined

[enjoy-digital]

Thanks @cklarhorst, sorry for the delay. I'll try to review and provide feedback soon.