phy/efinix: IO exclusion on DDROutput/Input now directly done in LiteX.

enjoy-digital · Aug 30, 2023 · 0f055b1 · 0f055b1
1 parent 8436d77
commit 0f055b1
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diff --git a/liteeth/phy/titaniumrgmii.py b/liteeth/phy/titaniumrgmii.py
@@ -38,8 +38,6 @@ def __init__(self, platform, pads, ddr_tx_ctl=True):
                 o   = pads.tx_data[n],
                 clk = "auto_eth_tx_clk", # FIXME.
             )
-        # FIXME: Integrate in EfinixDDROutputImpl.
-        platform.toolchain.excluded_ios.append(pads.tx_data)
 
         # TX Ctl IOs.
         # -----------
@@ -52,8 +50,6 @@ def __init__(self, platform, pads, ddr_tx_ctl=True):
                 o   = pads.tx_ctl,
                 clk = "auto_eth_tx_clk", # FIXME.
             )
-            # FIXME: Integrate in EfinixDDROutputImpl.
-            platform.toolchain.excluded_ios.append(pads.tx_ctl)
         else:
             self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
 
@@ -90,8 +86,6 @@ def __init__(self, platform, pads):
                 o2  = rx_data_l[n],
                 clk = "auto_eth_rx_clk", # FIXME.
             )
-        # FIXME: Integrate in EfinixDDROutputImpl.
-        platform.toolchain.excluded_ios.append(pads.rx_data)
 
         # RX Ctl IOs.
         # -----------

diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py
@@ -38,8 +38,6 @@ def __init__(self, platform, pads, ddr_tx_ctl=False):
                 o   = pads.tx_data[n],
                 clk = "auto_eth_tx_clk", # FIXME.
             )
-        # FIXME: Integrate in EfinixDDROutputImpl.
-        platform.toolchain.excluded_ios.append(pads.tx_data)
 
         # TX Ctl IOs.
         # -----------
@@ -52,8 +50,6 @@ def __init__(self, platform, pads, ddr_tx_ctl=False):
                 o   = pads.tx_ctl,
                 clk = "auto_eth_tx_clk", # FIXME.
             )
-            # FIXME: Integrate in EfinixDDROutputImpl.
-            platform.toolchain.excluded_ios.append(pads.tx_ctl)
         else:
             self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
 
@@ -90,8 +86,6 @@ def __init__(self, platform, pads):
                 o2  = rx_data_l[n],
                 clk = "auto_eth_rx_clk", # FIXME.
             )
-        # FIXME: Integrate in EfinixDDROutputImpl.
-        platform.toolchain.excluded_ios.append(pads.rx_data)
 
         # RX Ctl IOs.
         # -----------