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Issues: enjoy-digital/litedram

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#214 opened Aug 3, 2020 by enjoy-digital
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Issues list

Setting for user_clk question
#333 opened Apr 23, 2023 by ztachip
1
DDR4 reads without DQS at high speeds? question
#328 opened Feb 28, 2023 by alexey-morozov
1
--top-module 'sim' was not found in the design question
#325 opened Jan 28, 2023 by CarrolXC
5
Corresponding verilog testbench for ASIC question
#317 opened Jan 4, 2023 by CarrolXC
1
submodules verilog question
#316 opened Dec 26, 2022 by CarrolXC
2
Why are CL and CWL not included as speedgrade parameters in the module class? enhancement question
#306 opened Apr 15, 2022 by jaccharrison
1
LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements? bug? question
#303 opened Mar 28, 2022 by jaccharrison
8
Why is my simulation different to my target in regard to "address endianness"? question
#251 opened May 9, 2021 by nickoe
1
Wrong DQS pattern preamble/postamble bug? question
#225 opened Dec 10, 2020 by jedrzejboczar
2
Native Interface Documentation and Simulation add-answer-to-wiki enhancement question
#220 opened Oct 3, 2020 by vasimr
2
Core Question add-answer-to-wiki question
#219 opened Oct 2, 2020 by vasimr
4
ProTip! Exclude everything labeled bug with -label:bug.