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Please switch from setup-ghdl-ci to setup-ghdl

Status: Open.

#362 In enjoy-digital/litedram;

· Paebbels opened on Jan 12, 2025

Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO

bug?

Status: Open.

#358 In enjoy-digital/litedram;

· epsilon537 opened on May 6, 2024

Adding support to gowin phys in litedram.gen?

enhancement

Status: Open.

#357 In enjoy-digital/litedram;

· linhz0hz opened on Apr 28, 2024

LiteDRAMDMAWriter sinks data when not enabled

bug?

Status: Open.

#356 In enjoy-digital/litedram;

· DaveBerkeley opened on Apr 24, 2024

Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,

bug?

Status: Open.

#355 In enjoy-digital/litedram;

· fontamsoc opened on Mar 30, 2024

GENDDRPHY support?

Status: Open.

#353 In enjoy-digital/litedram;

· rhgndf opened on Jan 20, 2024

litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)

Status: Open.

#349 In enjoy-digital/litedram;

· jersey99 opened on Oct 5, 2023

DE10-Lite Memory initialization failed

Status: Open.

#347 In enjoy-digital/litedram;

· LearnShareAlways opened on Sep 6, 2023

Underclocking DRAM controler to increase access time

Status: Open.

#346 In enjoy-digital/litedram;

· denishoornaert opened on Aug 27, 2023

LiteDRAM core targeting DDR3 issues activate command twice for a write operation

Status: Open.

#345 In enjoy-digital/litedram;

· dinaabdelbaky opened on Aug 17, 2023

LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

Status: Open.

#344 In enjoy-digital/litedram;

· dinaabdelbaky opened on Aug 17, 2023

Axi port write data error

Status: Open.

#342 In enjoy-digital/litedram;

· Yuxin-Yu opened on Jun 7, 2023