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emu-russia · Mar 1, 2023 · eb4de0c · eb4de0c
1 parent c9f14d0
commit eb4de0c
Showing 1 changed file with 46 additions and 46 deletions.
diff --git a/Breaknes/BreaksCore/BogusBoard.cpp b/Breaknes/BreaksCore/BogusBoard.cpp
@@ -10,74 +10,74 @@ namespace Breaknes
 	BogusBoard::BogusBoard(APUSim::Revision apu_rev, PPUSim::Revision ppu_rev) : Board (apu_rev, ppu_rev)
 	{
 		core = new M6502Core::M6502(false, false);
-        wram = new BaseBoard::SRAM(wram_bits);
+		wram = new BaseBoard::SRAM(wram_bits);
 
-        for (int i = 0; i < wram->Dbg_GetSize(); i++)
-        {
-            wram->Dbg_WriteByte(i, 0);
-        }
+		for (int i = 0; i < wram->Dbg_GetSize(); i++)
+		{
+			wram->Dbg_WriteByte(i, 0);
+		}
 
-        AddBoardMemDescriptors();
-        AddDebugInfoProviders();
+		AddBoardMemDescriptors();
+		AddDebugInfoProviders();
 	}
 
 	BogusBoard::~BogusBoard()
 	{
 		delete core;
-        delete wram;
+		delete wram;
 	}
 
 	void BogusBoard::Step()
 	{
-        uint32_t wram_addr;
-        bool dz = false;
+		uint32_t wram_addr;
+		bool dz = false;
 
-        // Memory (Read)
+		// Memory (Read)
 
-        if (RnW == TriState::One)
-        {
-            wram_addr = addr_bus;
-            wram->sim(TriState::Zero, RnW, NOT(RnW), &wram_addr, &data_bus, dz);
-        }
+		if (RnW == TriState::One)
+		{
+			wram_addr = addr_bus;
+			wram->sim(TriState::Zero, RnW, NOT(RnW), &wram_addr, &data_bus, dz);
+		}
 
-        // Core
+		// Core
 
-        TriState inputs[(size_t)M6502Core::InputPad::Max]{};
-        TriState outputs[(size_t)M6502Core::OutputPad::Max];
+		TriState inputs[(size_t)M6502Core::InputPad::Max]{};
+		TriState outputs[(size_t)M6502Core::OutputPad::Max];
 
-        inputs[(size_t)M6502Core::InputPad::n_NMI] = n_NMI;
-        inputs[(size_t)M6502Core::InputPad::n_IRQ] = n_IRQ;
-        inputs[(size_t)M6502Core::InputPad::n_RES] = n_RES;
-        inputs[(size_t)M6502Core::InputPad::PHI0] = CLK;
-        inputs[(size_t)M6502Core::InputPad::RDY] = RDY;
-        inputs[(size_t)M6502Core::InputPad::SO] = SO;
+		inputs[(size_t)M6502Core::InputPad::n_NMI] = n_NMI;
+		inputs[(size_t)M6502Core::InputPad::n_IRQ] = n_IRQ;
+		inputs[(size_t)M6502Core::InputPad::n_RES] = n_RES;
+		inputs[(size_t)M6502Core::InputPad::PHI0] = CLK;
+		inputs[(size_t)M6502Core::InputPad::RDY] = RDY;
+		inputs[(size_t)M6502Core::InputPad::SO] = SO;
 
-        core->sim(inputs, outputs, &addr_bus, &data_bus);
+		core->sim(inputs, outputs, &addr_bus, &data_bus);
 
-        PHI1 = outputs[(size_t)M6502Core::OutputPad::PHI1];
-        PHI2 = outputs[(size_t)M6502Core::OutputPad::PHI2];
-        RnW = outputs[(size_t)M6502Core::OutputPad::RnW];
-        SYNC = outputs[(size_t)M6502Core::OutputPad::SYNC];
+		PHI1 = outputs[(size_t)M6502Core::OutputPad::PHI1];
+		PHI2 = outputs[(size_t)M6502Core::OutputPad::PHI2];
+		RnW = outputs[(size_t)M6502Core::OutputPad::RnW];
+		SYNC = outputs[(size_t)M6502Core::OutputPad::SYNC];
 
-        // Memory (Write)
+		// Memory (Write)
 
-        if (RnW == TriState::Zero)
-        {
-            wram_addr = addr_bus;
-            wram->sim(TriState::Zero, RnW, NOT(RnW), &wram_addr, &data_bus, dz);
-        }
+		if (RnW == TriState::Zero)
+		{
+			wram_addr = addr_bus;
+			wram->sim(TriState::Zero, RnW, NOT(RnW), &wram_addr, &data_bus, dz);
+		}
 
-        CLK = NOT(CLK);
+		CLK = NOT(CLK);
 
-        if (IsNegedge(PrevCLK, CLK))
-        {
-            phi_counter++;
-        }
-        PrevCLK = CLK;
+		if (IsNegedge(PrevCLK, CLK))
+		{
+			phi_counter++;
+		}
+		PrevCLK = CLK;
 	}
 
-    size_t BogusBoard::GetPHICounter()
-    {
-        return phi_counter;
-    }
+	size_t BogusBoard::GetPHICounter()
+	{
+		return phi_counter;
+	}
 }