Description
Many (even combinational) circuits have efficient descriptions, but become impracticable when they have to be "flattened" or unrolled. This is discussed in detail in e.g. [KMsB13] and [SHSSK15].
The Bristol Format circuits which this library accepts have to be totally flattened. While this makes things easier for the developer (you), it significantly limits the circuits / functions on which the protocol can operate efficiently in practice. Moreover, the Bristol format makes it difficult to use modern hardware synthesis tools. Indeed, the only tool I could find which specifically targets this format is CBMC-GC-2, which is a bit buggy and performs poorly (huge memory consumption even on medium-sized circuits).
As a longer-term goal, I wonder if it would be possible to shift to a more modern / efficient circuit representation. For example, we could target the format output by yosys after running the sequence of commands
proc; opt; techmap; opt; abc; opt; write_verilog out.v
I recognize this would be a very large project, but I think it would significantly enhance the practical power of EMP-Toolkit, and could be worthwhile. I'd be happy to contribute.