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[FIRRTL][LowerAnnotations] Fix non-probe type compat check. (llvm#6822)
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Compatibility dest/source operands were backwards,
introduced in llvm#4656 .

Add test as "legacy wiring" as non-ref-type-port path is a hidden option.

Fixes llvm#6819.
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dtzSiFive authored Mar 14, 2024
1 parent 9c4f721 commit b6f50d6
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Showing 2 changed files with 30 additions and 1 deletion.
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -858,7 +858,7 @@ LogicalResult LowerAnnotationsPass::solveWiringProblems(ApplyState &state) {
// Otherwise they must be identical or FIRRTL type-equivalent
// (connectable).
if (sourceFType != sinkFType &&
!areTypesEquivalent(sourceFType, sinkFType)) {
!areTypesEquivalent(sinkFType, sourceFType)) {
auto diag = mlir::emitError(source.getLoc())
<< "Wiring Problem source type " << sourceType
<< " does not match sink type " << sinkType;
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29 changes: 29 additions & 0 deletions test/Dialect/FIRRTL/legacy-wiring.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -206,3 +206,32 @@ firrtl.circuit "IntWidths" attributes {
firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint
}
}

// -----

// Check direction of compatibility using const/non-const issue encountered (#6819).
firrtl.circuit "Issue6819" attributes {
rawAnnotations = [
{
class = "firrtl.passes.wiring.SourceAnnotation",
target = "~Issue6819|Bar>y",
pin = "xyz"
},
{
class = "firrtl.passes.wiring.SinkAnnotation",
target = "~Issue6819|Issue6819>x",
pin = "xyz"
}
]} {
firrtl.module private @Bar() {
%y = firrtl.wire interesting_name : !firrtl.const.uint<4>
}
// CHECK-LABEL: module @Issue6819
firrtl.module @Issue6819() {
// CHECK: firrtl.connect %x, %{{[^ ]*}} : !firrtl.uint, !firrtl.const.uint<4>
firrtl.instance bar interesting_name @Bar()
%x = firrtl.wire interesting_name : !firrtl.uint
%invalid_ui1 = firrtl.invalidvalue : !firrtl.uint
firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint
}
}

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