Add more tests to deal with issue ESCOMP#2219, add a test that turns …

…excess ice off, add tests to expected fails
ekluzek · Oct 21, 2023 · c1cadb3 · c1cadb3
1 parent da5beb8
commit c1cadb3
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diff --git a/cime_config/testdefs/ExpectedTestFails.xml b/cime_config/testdefs/ExpectedTestFails.xml
@@ -28,6 +28,21 @@
   -->
 
 
+  <!-- cesm3_dev test suite failures -->
+  <test name="PEM_D_Ld9.ne30pg3_t232.I1850Clm51BgcCrop.derecho_intel.clm-clm51cam6LndTuningMode">
+    <phase name="COMPARE_base_modpes">
+      <status>FAIL</status>
+      <issue>#2210</issue>
+    </phase>
+  </test>
+  <test name="ERP_D_Ld9.ne30pg3_t232.I1850Clm51BgcCrop.derecho_intel.clm-clm51cam6LndTuningMode">
+    <phase name="COMPARE_base_rest">
+      <status>FAIL</status>
+      <issue>#2210</issue>
+    </phase>
+  </test>
+
+
   <!-- aux_clm test suite failures -->
   <test name="SMS_D_Ld1_Mmpi-serial_Vmct.f45_f45_mg37.I2000Clm50SpRs.izumi_gnu.clm-ptsRLA">
     <phase name="SHAREDLIB_BUILD">

diff --git a/cime_config/testdefs/testlist_clm.xml b/cime_config/testdefs/testlist_clm.xml
@@ -62,6 +62,33 @@
       <option name="comment">CESM3 development Exact restart test with change in the processor count at the standard coupled resolution</option>
     </options>
   </test>
+  <test name="PEM_D_Ld9" grid="ne30pg3_t232" compset="I1850Clm51BgcCrop" testmods="clm/clm51cam6LndTuningMode">
+    <machines>
+      <machine name="derecho" compiler="intel" category="cesm3_dev"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment">CESM3 development test with change in the processor count at the standard coupled resolution</option>
+    </options>
+  </test>
+  <test name="PEM_D_Ld9" grid="ne30pg3_t232" compset="I1850Clm51BgcCrop" testmods="clm/clm51cam6LndTuningModeNoExIce">
+    <machines>
+      <machine name="derecho" compiler="intel" category="cesm3_dev"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment">CESM3 development test with change in the processor count at the standard coupled resolution, wihout excess-ice</option>
+    </options>
+  </test>
+  <test name="ERS_D_Ld9" grid="ne30pg3_t232" compset="I1850Clm51BgcCrop" testmods="clm/clm51cam6LndTuningMode">
+    <machines>
+      <machine name="derecho" compiler="intel" category="cesm3_dev"/>
+    </machines>
+    <options>
+      <option name="wallclock">00:20:00</option>
+      <option name="comment">CESM3 development simple exact restart test with change in the processor count at the standard coupled resolution</option>
+    </options>
+  </test>
   <test name="ERI_D" grid="ne30pg3_t232" compset="I1850Clm51BgcCrop" testmods="clm/clm51cam6LndTuningMode">
     <machines>
       <machine name="derecho" compiler="intel" category="cesm3_dev"/>

diff --git a/cime_config/testdefs/testmods_dirs/clm/clm51cam6LndTuningModeNoExIce/include_user_mods b/cime_config/testdefs/testmods_dirs/clm/clm51cam6LndTuningModeNoExIce/include_user_mods
@@ -0,0 +1 @@
+../clm51cam6LndTuningMode/
diff --git a/cime_config/testdefs/testmods_dirs/clm/clm51cam6LndTuningModeNoExIce/user_nl_clm b/cime_config/testdefs/testmods_dirs/clm/clm51cam6LndTuningModeNoExIce/user_nl_clm
@@ -0,0 +1,3 @@
+! Turn off excess ice
+use_exice = .true.
+use_exice_streams = .true.