Pong on FPGA

Overview

This is a VHDL implementation of 1D Pong for the Basys3 board. The playing field is mapped to a single-dimensional array of 16 LEDs and the left/right buttons act as paddles. The lit up LED represents the ball moving across the field.

How It Works

• Gameplay: Players hit the paddle button when the ball (LED) reaches their end. Early/late hits end the round and score a point for the opponent.
• Speed: On each successful return, the ball speed is incremented. By default, the initial speed is 2 LEDs/sec and is incremented at a rate of 1 LED/sec per level. And there are a total of 7 levels. The initial speed and increment is parameterized by the INITIAL_SPEED and SPEED_INCREMENT generics.
• Serving: Serve alternates every round, regardless of who won the previous point.
• Scoring: By default, first to 7 points with a 2-point lead wins. Scores (up to 99) are shown on the seven-segment displays. Parameterized by the MIN_WIN_SCORE and WIN_BY_SCORE generics.
• Victory: LEDs show a victory pattern at the end of each round. The pattern shown depends on who won that round and lasts for 1 sec by default. This can be configured by setting the LEFT_WIN_PATTERN, RIGHT_WIN_PATTERN, and PATTERN_PERIOD generics.
• Reset: The down button resets the game.

Design Diagrams

State Machine

Made with obsidian canvas.

Design Block

Made with excalidraw.

Toplevel(wrapper) Block

Made with excalidraw.

Authors/Course Info

• Abhijeet Surakanti, Salini Ambadapudi, Gurbir Singh.
• Final project for CPE 3020: VHDL Design with FPGAs (Summer 2025).