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@egk696
egk696 committed Oct 2, 2020
1 parent b2a334d commit 794ddf9
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Showing 7 changed files with 143 additions and 118 deletions.
4 changes: 2 additions & 2 deletions build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ name := "an-ethernet-controller"

version := "3.1.1"

scalaVersion := "2.11.7"
scalaVersion := "2.11.8"

scalacOptions ++= Seq("-unchecked", "-deprecation", "-feature", "-language:reflectiveCalls")

Expand All @@ -22,4 +22,4 @@ resolvers ++= Seq(
libraryDependencies += "edu.berkeley.cs" %% "chisel" % "2.2.38"

//libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.1.2"
//libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.2.2"
//libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.2.2"
96 changes: 42 additions & 54 deletions src/main/scala/ethcontroller/design/EthTxController.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module
*/
val constRamIdWidth = log2Ceil(numFrameBuffers)
val constRamAddrWidth = log2Ceil(EthernetConstants.constEthFrameLength)
val stWait :: stSoF :: stTxPreamble :: stTxFrame :: stTxFCS :: stIFG :: stEoF :: Nil = Enum(UInt(), 7)
val stWait :: stTxPreamble :: stTxFrame :: stTxFCS :: stIFG :: stEoF :: Nil = Enum(UInt(), 6)
val miiTx = Module(new MIITx())

/**
Expand Down Expand Up @@ -62,22 +62,20 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module

val ethTxCtrlRegMap = Map(
"txEn" -> Map("Reg" -> txEnReg, "Addr" -> Bits("h00")), //0x0
"frameSize" -> Map("Reg" -> txFrameSizeReg, "Addr" -> Bits("h01")), //0x4
"fifoCount" -> Map("Reg" -> fifoCountReg, "Addr" -> Bits("h02")), //0x8
"fifoEmpty" -> Map("Reg" -> fifoEmptyReg, "Addr" -> Bits("h03")), //0xC
"fifoFull" -> Map("Reg" -> fifoFullReg, "Addr" -> Bits("h04")), //0x10
"fifoPop" -> Map("Reg" -> fifoPopReg, "Addr" -> Bits("h05")), //0x14
"fifoPush" -> Map("Reg" -> fifoPushReg, "Addr" -> Bits("h06")), //0x18
"macFilter" -> Map("Reg" -> macRxFilterReg, "Addr" -> Bits("h07")) //0x1C
"frameSize" -> Map("Reg" -> txFrameSizeReg, "Addr" -> Bits("h04")), //0x4
"fifoCount" -> Map("Reg" -> fifoCountReg, "Addr" -> Bits("h08")), //0x8
"fifoEmpty" -> Map("Reg" -> fifoEmptyReg, "Addr" -> Bits("h0C")), //0xC
"fifoFull" -> Map("Reg" -> fifoFullReg, "Addr" -> Bits("h10")), //0x10
"fifoPop" -> Map("Reg" -> fifoPopReg, "Addr" -> Bits("h14")), //0x14
"fifoPush" -> Map("Reg" -> fifoPushReg, "Addr" -> Bits("h18")), //0x18
"macFilter" -> Map("Reg" -> macRxFilterReg, "Addr" -> Bits("h1C")) //0x1C
)

val preambleReg = Reg(init = UInt(EthernetConstants.constSFD, width = 64))
val fcsReg = Reg(init = UInt(0, width = 16))

val miiStartTxReg = Reg(init = false.B)
val miiEndTxReg = Reg(init = false.B)
val miiByteData = Wire(init = UInt(0, width = 8))
val miiByteLoad = Wire(init = false.B)
val miiByteDataReg = Reg(init = UInt(0, width = 8))
val miiByteLoadReg = Reg(init = false.B)
val miiIsReady = Wire(init = false.B)

/**
Expand All @@ -91,26 +89,20 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module
val validRamPush = fifoPushReg === true.B && !fifoFullReg

//Reset regs to default values
miiStartTxReg := false.B
miiEndTxReg := false.B
fifoPushReg := false.B
fifoPopReg := false.B
miiByteLoadReg := false.B
//State Machine
switch(stateReg) {
is(stWait) { //wait for available data in FIFORam
when(!fifoEmptyReg) {
stateReg := stSoF
}
}
is(stSoF) { //wait until miiIsReady
when(miiIsReady) {
miiStartTxReg := true.B
stateReg := stTxPreamble
}
}
is(stTxPreamble) {
when(miiIsReady) { //wait until miiIsReady and then countup the PREAMBLE
when(miiIsReady & ~miiByteLoadReg) { //wait until miiIsReady and then countup the PREAMBLE
when(byteCntReg < 8.U) {
miiByteLoadReg := true.B
byteCntReg := byteCntReg + 1.U
}.otherwise {
byteCntReg := 0.U
Expand Down Expand Up @@ -143,8 +135,6 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module
}
}
is(stEoF) {
miiByteData := 0.U
miiEndTxReg := true.B
stateReg := stIFG
}
is(stIFG) {
Expand All @@ -158,32 +148,32 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module
}
}

when(validRamPush) {
wrRamIdReg := wrRamIdReg + 1.U
fifoCountReg := fifoCountReg + 1.U
}

when(validRamPop) {
rdRamIdReg := rdRamIdReg + 1.U
fifoCountReg := fifoCountReg - 1.U
}

when(validRamPush) {
wrRamIdReg := wrRamIdReg + 1.U
fifoCountReg := fifoCountReg + 1.U
}

/**
* Multiplexing MII byte source
*/
miiByteLoad := stateReg === stTxPreamble || stateReg === stTxFCS || (stateReg === stTxFrame && ramRespReg === OcpResp.DVA)
miiByteData := Mux(stateReg === stTxFCS, preambleReg(8.U + 8.U * byteCntReg - 1.U, 8.U * byteCntReg),
Mux(stateReg === stTxFCS, fcsReg(8.U + 8.U * byteCntReg - 1.U, 8.U * byteCntReg), ramDataReg))
miiByteDataReg := RegNext(Mux(stateReg === stTxFCS, preambleReg(8.U + 8.U * byteCntReg - 1.U, 8.U * byteCntReg),
Mux(stateReg === stTxFCS, fcsReg(8.U + 8.U * byteCntReg - 1.U, 8.U * byteCntReg), ramDataReg)))


/**
* Ram master-port Control
*/
for (ramId <- 0 until numFrameBuffers) {
ramMasterRegs(ramId).Cmd := (Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Cmd, Mux(ethRamRdEn, OcpCmd.RD, OcpCmd.IDLE)))
ramMasterRegs(ramId).Addr := (Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Addr(constRamAddrWidth - 1, 2), byteCntReg(constRamAddrWidth - 1, 2)))
ramMasterRegs(ramId).ByteEn := (Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.ByteEn, UIntToOH(byteCntReg(1, 0), width = 4)))
ramMasterRegs(ramId).Data := (ocpMasterReg.Data)
ramMasterRegs(ramId).Cmd := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Cmd, Mux(ethRamRdEn, OcpCmd.RD, OcpCmd.IDLE))
ramMasterRegs(ramId).Addr := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Addr(constRamAddrWidth - 1, 2), byteCntReg(constRamAddrWidth - 1, 2))
ramMasterRegs(ramId).ByteEn := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.ByteEn, UIntToOH(byteCntReg(1, 0), width = 4))
ramMasterRegs(ramId).Data := ocpMasterReg.Data
}

/**
Expand All @@ -202,42 +192,42 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module
}.otherwise {
when(ocpMasterReg.Cmd === OcpCmd.RD) {
ocpRespReg := OcpResp.DVA
when(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("txEn")("Addr")) {
when(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("txEn")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("txEn")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("frameSize")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("frameSize")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("frameSize")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoCount")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoCount")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("fifoCount")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoEmpty")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoEmpty")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("fifoEmpty")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoFull")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoFull")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("fifoFull")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoPop")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoPop")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("fifoPop")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoPush")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoPush")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("fifoPush")("Reg")
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("macFilter")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("macFilter")("Addr")) {
ocpDataReg := ethTxCtrlRegMap("macFilter")("Reg")
}
}.elsewhen(ocpMasterReg.Cmd === OcpCmd.WR) {
when(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("txEn")("Addr")) {
when(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("txEn")("Addr")) {
ethTxCtrlRegMap("txEn")("Reg") := orR(ocpMasterReg.Data)
ocpRespReg := OcpResp.DVA
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("frameSize")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("frameSize")("Addr")) {
ethTxCtrlRegMap("frameSize")("Reg") := ocpDataReg
ocpRespReg := OcpResp.DVA
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoCount")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoCount")("Addr")) {
ocpRespReg := OcpResp.ERR
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoEmpty")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoEmpty")("Addr")) {
ocpRespReg := OcpResp.ERR
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoFull")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoFull")("Addr")) {
ocpRespReg := OcpResp.ERR
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoPop")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoPop")("Addr")) {
ocpRespReg := OcpResp.ERR
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("fifoPush")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoPush")("Addr")) {
ethTxCtrlRegMap("fifoPush")("Reg") := orR(ocpMasterReg.Data) //set on write and reset in the next clock cycle
ocpRespReg := OcpResp.DVA //is the responsibility of the master to check first the count ?
}.elsewhen(ocpMasterReg.Addr(4, 2) === ethTxCtrlRegMap("macFilter")("Addr")) {
}.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("macFilter")("Addr")) {
ethTxCtrlRegMap("macFilter")("Reg") := ocpMasterReg.Data
ocpRespReg := OcpResp.DVA
}
Expand All @@ -252,10 +242,8 @@ class EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module
io.ocp.S.Data := ocpDataReg
io.ocp.S.Resp := ocpRespReg
miiIsReady := miiTx.io.ready
miiTx.io.startTx := miiStartTxReg
miiTx.io.endTx := miiEndTxReg
miiTx.io.macDataDv := miiByteLoad
miiTx.io.macData := miiByteData
miiTx.io.macDataDv := miiByteLoadReg
miiTx.io.macData := miiByteDataReg
miiTx.io.miiChannel <> io.miiChannel
for (ramId <- 0 until numFrameBuffers) {
io.ramPorts(ramId).M := ramMasterRegs(ramId)
Expand Down
4 changes: 1 addition & 3 deletions src/main/scala/ethcontroller/design/MIITx.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,6 @@ import ethcontroller.utils.{ExtClockSampler, Serializer}
class MIITx extends Module {
val io = new Bundle() {
val miiChannel = new MIIChannel()
val startTx = Bool(INPUT)
val endTx = Bool(INPUT)
val macDataDv = Bool(INPUT)
val macData = Bits(INPUT, width = 8)
val ready = Bool(OUTPUT)
Expand Down Expand Up @@ -49,7 +47,7 @@ class MIITx extends Module {

when(~transmittingReg && serializeByteToNibble.io.dv) {
transmittingReg := true.B
}.elsewhen(io.endTx && serializeByteToNibble.io.done) {
}.elsewhen(~serializeByteToNibble.io.dv && serializeByteToNibble.io.done) {
transmittingReg := false.B
}

Expand Down
5 changes: 5 additions & 0 deletions src/main/scala/ethcontroller/protocols/EthernetFrame.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ abstract class EthernetFrame {
val dstMac: Array[Byte]
val srcMac: Array[Byte]
val ethType: Array[Byte]
val data: Array[Byte]

//Special cases
val ipHeader: Array[Byte]
val udpHeader: Array[Byte]
val ptpHeader: Array[Byte]
Expand All @@ -34,6 +37,8 @@ abstract class EthernetFrame {

def ethTypeNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ethType, msbFirst = false)

def dataNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(data, msbFirst = false)

def ipHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ipHeader, msbFirst = false)

def udpHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(udpHeader, msbFirst = false)
Expand Down
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