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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,87 @@ | ||
| package ethcontroller.design | ||
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| import Chisel._ | ||
| import ethcontroller.interfaces.MIIChannel | ||
| import ethcontroller.utils.Serializer | ||
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| class MIITx extends Module { | ||
| val io = new Bundle() { | ||
| val miiChannel = new MIIChannel() | ||
| val startTx = Bool(INPUT) | ||
| val endTx = Bool(INPUT) | ||
| val busy = Bool(OUTPUT) | ||
| val macDataDv = Bool(INPUT) | ||
| val macData = Bits(INPUT, width = 64) | ||
| val phyErr = Bool(OUTPUT) | ||
| } | ||
|
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| /** | ||
| * Registers and components | ||
| */ | ||
| val busyReg = Reg(init = false.B) | ||
| val startTxReg = Reg(init = false.B) | ||
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| val serializeDataToByte = Module(new Serializer(false, 64, 8)) | ||
| val serializeByteToNibble = Module(new Serializer(false, 8, 4)) | ||
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| /** | ||
| * Sampling clock and line of MII | ||
| */ | ||
| val miiClkReg = Reg(next = io.miiChannel.clk) | ||
| val miiClkReg2 = Reg(next = miiClkReg) | ||
| val miiErrReg = Reg(next = io.miiChannel.err) | ||
| val miiErrReg2 = Reg(next = miiErrReg) | ||
| val miiDataReg = Reg(init = UInt(0, width = 4)) | ||
| val miiDvReg = Reg(init = false.B) | ||
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| /** | ||
| * Flags | ||
| */ | ||
| val phyNA = io.miiChannel.col & ~io.miiChannel.crs | ||
| val phyError = phyNA || miiErrReg2 | ||
| val fallingMIIEdge = ~miiClkReg & miiClkReg2 //we check the falling so that when the rising arrives on the next rising the data will be available to the PHY | ||
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| /** | ||
| * Serialize Preamble to Byte | ||
| */ | ||
| serializeDataToByte.io.load := io.macDataDv | ||
| serializeDataToByte.io.shiftIn := io.macData | ||
| serializeDataToByte.io.en := ~serializeByteToNibble.io.dv | ||
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| /** | ||
| * Serialize Output to Nibble | ||
| */ | ||
| serializeByteToNibble.io.load := serializeDataToByte.io.dv | ||
| serializeByteToNibble.io.shiftIn := serializeDataToByte.io.shiftOut | ||
| serializeByteToNibble.io.en := fallingMIIEdge | ||
|
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| /** | ||
| * Interface control and automatic PREAMBLE/IFG injection | ||
| */ | ||
| when(io.startTx) { | ||
| busyReg := true.B | ||
| }.elsewhen(RegNext(serializeDataToByte.io.done) && RegNext(serializeByteToNibble.io.done)) { | ||
| busyReg := false.B | ||
| } | ||
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| when(fallingMIIEdge) { | ||
| //(De-)Assert MII data valid | ||
| when(busyReg) { | ||
| miiDvReg := true.B | ||
| }.elsewhen(~busyReg) { | ||
| miiDvReg := false.B | ||
| } | ||
| //Data nibble | ||
| miiDataReg := serializeByteToNibble.io.shiftOut | ||
| } | ||
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| /** | ||
| * I/O plumbing | ||
| */ | ||
| io.busy := serializeDataToByte.io.dv | ||
| io.phyErr := phyNA | ||
| io.miiChannel.data := miiDataReg | ||
| io.miiChannel.dv := miiDvReg | ||
|
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| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,18 +1,20 @@ | ||
| // See README.md for license details. | ||
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| package ethcontroller.interfaces | ||
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| import Chisel.{Bits, Bool, Bundle, INPUT} | ||
| import Chisel.{Bits, Bool, Bundle, INPUT, OUTPUT} | ||
|
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| class MIIChannel extends Bundle{ | ||
| class MIIChannel extends Bundle { | ||
| /** Clock from the PHY */ | ||
| val clk = Bool(INPUT) | ||
| /** Received data valid */ | ||
| val dv = Bool() | ||
| val dv = Bool(OUTPUT) | ||
| /** Received nibble data */ | ||
| val data = Bits(width=4) | ||
| val data = Bits(OUTPUT,width = 4) | ||
| /** Signal could not be decoded to data */ | ||
| val err = Bool() | ||
| val err = Bool(INPUT) | ||
| /** Carrier-sense signal */ | ||
| val crs = Bool() | ||
| val crs = Bool(INPUT) | ||
| /** Collision detection signal */ | ||
| val col = Bool() | ||
| val col = Bool(INPUT) | ||
| } |
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