platform: add radxa e25 support

Signed-off-by: Nascs <nascs@radxa.com>
eclipse · Jan 23, 2024 · 60d99f1 · 60d99f1
1 parent 3022803
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diff --git a/README.md b/README.md
@@ -46,6 +46,7 @@ ARM
 * [96Boards](../master/docs/96boards.md)
 * [ADLINK IPi-SMARC ARM](../master/docs/adlink_ipi_arm.md)
 * [Radxa CM3](../master/docs/radxa_cm3.md)
+* [Radxa E25](../master/docs/radxa_e25.md)
 * [Radxa ROCK 3A](../master/docs/radxa_rock_3a.md)
 * [Radxa ROCK 3B](../master/docs/radxa_rock_3b.md)
 * [Radxa ROCK 3C](../master/docs/radxa_rock_3c.md)

diff --git a/api/mraa/types.h b/api/mraa/types.h
@@ -78,6 +78,7 @@ typedef enum {
     MRAA_RADXA_CM3 = 33,            /**< Radxa CM3 */
     MRAA_RADXA_CM5_IO = 34,         /**< Radxa CM5 IO */
     MRAA_RADXA_ROCK_3A = 35,        /**< Radxa ROCK 3 Model A */
+    MRAA_RADXA_E25 = 36,            /**< Radxa E25 */
 
     // USB platform extenders start at 256
     MRAA_FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */
@@ -416,6 +417,30 @@ typedef enum {
     MRAA_RADXA_CM3_IO_PIN40 = 40
 } mraa_radxa_cm3_io_wiring_t;
 
+/**
+ *  Radxa E25 GPIO numbering enum
+ */
+typedef enum {
+    MRAA_RADXA_E25_PIN3 = 3,
+    MRAA_RADXA_E25_PIN5 = 5,
+    MRAA_RADXA_E25_PIN7 = 7,
+    MRAA_RADXA_E25_PIN8 = 8,
+    MRAA_RADXA_E25_PIN10 = 10,
+    MRAA_RADXA_E25_PIN11 = 11,
+    MRAA_RADXA_E25_PIN12 = 12,
+    MRAA_RADXA_E25_PIN13 = 13,
+    MRAA_RADXA_E25_PIN15 = 15,
+    MRAA_RADXA_E25_PIN16 = 16,
+    MRAA_RADXA_E25_PIN17 = 17,
+    MRAA_RADXA_E25_PIN18 = 18,
+    MRAA_RADXA_E25_PIN19 = 19,
+    MRAA_RADXA_E25_PIN21 = 21,
+    MRAA_RADXA_E25_PIN22 = 22,
+    MRAA_RADXA_E25_PIN23 = 23,
+    MRAA_RADXA_E25_PIN24 = 24,
+    MRAA_RADXA_E25_PIN26 = 26
+} mraa_radxa_e25_wiring_t;
+
 /**
  *  ROCKPI4 GPIO numbering enum
  */

diff --git a/api/mraa/types.hpp b/api/mraa/types.hpp
@@ -72,6 +72,7 @@ typedef enum {
     RADXA_CM3 = 33,            /**< Radxa CM3 */
     RADXA_CM5_IO = 34,         /**< Radxa CM5 IO */
     RADXA_ROCK_3A = 35,        /**< Radxa ROCK 3 Model A */
+    RADXA_E25 = 36,            /**< Radxa E25 */
 
     FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */
 
@@ -407,6 +408,30 @@ typedef enum {
     RADXA_CM3_IO_PIN40 = 40
 } RadxaCM3IOWiring;
 
+/**
+ *  Radxa E25 GPIO numbering enum
+ */
+typedef enum {
+    RADXA_E25_PIN3 = 3,
+    RADXA_E25_PIN5 = 5,
+    RADXA_E25_PIN7 = 7,
+    RADXA_E25_PIN8 = 8,
+    RADXA_E25_PIN10 = 10,
+    RADXA_E25_PIN11 = 11,
+    RADXA_E25_PIN12 = 12,
+    RADXA_E25_PIN13 = 13,
+    RADXA_E25_PIN15 = 15,
+    RADXA_E25_PIN16 = 16,
+    RADXA_E25_PIN17 = 17,
+    RADXA_E25_PIN18 = 18,
+    RADXA_E25_PIN19 = 19,
+    RADXA_E25_PIN21 = 21,
+    RADXA_E25_PIN22 = 22,
+    RADXA_E25_PIN23 = 23,
+    RADXA_E25_PIN24 = 24,
+    RADXA_E25_PIN26 = 26
+} RadxaE25Wiring;
+
 /**
  *  ROCKPI4 GPIO numbering enum
  */

diff --git a/docs/index.java.md b/docs/index.java.md
@@ -55,6 +55,7 @@ Specific platform information for supported platforms is documented here:
 - @ref up-xtreme
 - @ref _orange_pi_prime
 - @ref radxa_cm3
+- @ref radxa_e25
 - @ref radxa_cm5_io
 - @ref radxa_rock_3a
 - @ref radxa_rock_3b

diff --git a/docs/index.md b/docs/index.md
@@ -63,6 +63,7 @@ Specific platform information for supported platforms is documented here:
 - @ref upXtreme
 - @ref _orange_pi_prime
 - @ref radxa_cm3
+- @ref radxa_e25
 - @ref radxa_cm5_io
 - @ref radxa_rock_3a
 - @ref radxa_rock_3b

diff --git a/docs/radxa_e25.md b/docs/radxa_e25.md
@@ -0,0 +1,40 @@
+Radxa E25 {#_Radxa}
+====================
+
+Radxa E25 is a Rockchip RK3568 based SBC(Single Board Computer) by Radxa. It can run Android or Linux. Radxa E25 features a four core ARM processor, 64bit dual channel 3200Mb/s LPDDR4, HDMI up to 4K60p, MIPI DSI, MIPI CSI, 3.5mm combo audio jack, Wi-Fi 6, Bluetooth 5.0, USB, GbE LAN, and 40-pin color expansion header. Radxa E25 is powered by the USB Type-C port, and supports 5V input only. The recommended power adapter is 5V/3A without SSD, or 5V/5A with SSD.
+
+Interface notes
+---------------
+
+- All UART ports support baud up to 1500000.
+- Radxa E25 v1.3 or earlier with 10-pin header are **NOT** supported. Only v1.4 or later with 26-pin header are supported.
+
+Pin Mapping
+-----------
+
+Radxa E25 has a 40-pin expansion header. Each pin is distinguished by the color.
+
+|    Function5|    Function4|  Function3|  Function2|  Function1|  PIN  |  PIN  |  Function1|    Function2|  Function3|   Function4|   Function5|
+|-------------|-------------|-----------|-----------|-----------|:------|------:|-----------|-------------|-----------|------------|------------|
+|             |             |           |           |  3V3      |   1   |   2   |    +5.0V  |             |           |            |            |
+|             |             |I2C3_SDA_M0|UART3_RX_M0|GPIO1_A0   |   3   |   4   |    +5.0V  |             |           |            |            |
+|             |             |I2C3_SCL_M0|UART3_TX_M0|GPIO1_A1   |   5   |   6   |     GND   |             |           |            |            |
+|             |PWM12_M0     |           |UART3_TX_M1|GPIO3_B7   |   7   |   8   |   GPIO3_C2|  UART5_TX_M1|           |            |SPI1_MISO_M1|
+|             |             |           |           |  GND      |   9   |   10  |   GPIO3_C3|  UART5_RX_M1|           |            | SPI1_CLK_M1|
+|             |PWM14_M0     |           |UART7_TX_M1|GPIO3_C4   |   11  |   12  |   GPIO3_A3|             |           |            |            |
+|             |             |           |UART7_RX_M1|GPIO3_C5   |   13  |   14  |     GND   |             |           |            |            |
+|SPI1_MOSI_M1 |             |           |           |GPIO3_C1   |   15  |   16  |   GPIO2_D2|             |           |            | SPI0_CSO_M1|
+|SPI1_CSO_M1  |             |           |           |GPIO3_A1   |   17  |   18  |   GPIO0_C6|             |           |     PWM7_IR| SPI0_CS0_M0|
+|SPI0_MOSI_M1 |             |           |           |GPIO2_D1   |   19  |   20  |    GND    |             |           |            |            |
+|SPI0_MISO_M1 |             |           |           |GPIO2_D0   |   21  |   22  |SARADC_VIN5|             |           |            |            |
+|SPI0_CLK_M1  |             |           |           |GPIO2_D3   |   23  |   24  |   GPIO4_C6|             |           |    PWM13_M1|            |
+|             |             |           |           |  GND      |   25  |   26  |   GPIO3_C0|  UART3_RX_M1|           |    PWM13_M0|            |
+
+Supports
+--------
+
+You can find additional product support in the following channels:
+
+- [Product Info](https://docs.radxa.com/en/rock3/e25)
+- [Forums](https://forum.radxa.com/c/rock3)
+- [Github](https://github.com/radxa)
diff --git a/include/arm/radxa_e25.h b/include/arm/radxa_e25.h
@@ -0,0 +1,30 @@
+/*
+ * Author: Nascs <nascs@radxa.com>
+ * Copyright (c) 2023 Radxa Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mraa_internal.h"
+
+#define MRAA_RADXA_E25_GPIO_COUNT 17
+#define MRAA_RADXA_E25_I2C_COUNT  1
+#define MRAA_RADXA_E25_SPI_COUNT  2
+#define MRAA_RADXA_E25_UART_COUNT 3
+#define MRAA_RADXA_E25_PWM_COUNT  6
+#define MRAA_RADXA_E25_AIO_COUNT  1
+#define MRAA_RADXA_E25_PIN_COUNT  26
+#define PLATFORM_NAME_RADXA_E25   "Radxa E25 Carrier Board"
+
+mraa_board_t *
+        mraa_radxa_e25();
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
@@ -111,6 +111,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
   ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3b.c
   ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c
   ${PROJECT_SOURCE_DIR}/src/arm/radxa_cm3.c
+  ${PROJECT_SOURCE_DIR}/src/arm/radxa_e25.c
   ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c
   ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5b.c
   ${PROJECT_SOURCE_DIR}/src/arm/radxa_cm5_io.c

diff --git a/src/arm/arm.c b/src/arm/arm.c
@@ -11,6 +11,7 @@
 
 #include "arm/96boards.h"
 #include "arm/radxa_cm3.h"
+#include "arm/radxa_e25.h"
 #include "arm/radxa_rock_3a.h"
 #include "arm/radxa_rock_3b.h"
 #include "arm/radxa_rock_3c.h"
@@ -103,6 +104,8 @@ mraa_arm_platform()
                  mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_IO_2) ||
                  mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO))
             platform_type = MRAA_RADXA_CM3;
+        else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_E25))
+            platform_type = MRAA_RADXA_E25;
         else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3A))
             platform_type = MRAA_RADXA_ROCK_3A;
         else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3B))
@@ -149,6 +152,9 @@ mraa_arm_platform()
         case MRAA_RADXA_CM3:
             plat = mraa_radxa_cm3();
             break;
+        case MRAA_RADXA_E25:
+            plat = mraa_radxa_e25();
+            break;
         case MRAA_RADXA_ROCK_3A:
             plat = mraa_radxa_rock_3a();
             break;

diff --git a/src/arm/radxa_e25.c b/src/arm/radxa_e25.c
@@ -0,0 +1,141 @@
+/*
+ * Author: Nascs <nascs@radxa.com>
+ * Copyright (c) 2023 Radxa Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include <mraa/common.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include "arm/radxa_e25.h"
+#include "common.h"
+
+const char* radxa_e25_serialdev[MRAA_RADXA_E25_UART_COUNT] = { "/dev/ttyS3", "/dev/ttyS5", "/dev/ttyS7" };
+
+void
+mraa_radxa_e25_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name)
+{
+
+    if (index > board->phy_pin_count)
+        return;
+
+    mraa_pininfo_t* pininfo = &board->pins[index];
+    strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE);
+
+    if (pincapabilities_t.gpio == 1) {
+        pininfo->gpio.gpio_chip = gpio_chip;
+        pininfo->gpio.gpio_line = gpio_line;
+    }
+
+    pininfo->capabilities = pincapabilities_t;
+
+    pininfo->gpio.mux_total = 0;
+}
+
+mraa_board_t*
+mraa_radxa_e25()
+{
+    mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
+    if (b == NULL) {
+        return NULL;
+    }
+
+    b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
+    if (b->adv_func == NULL) {
+        free(b);
+        return NULL;
+    }
+
+    // pin mux for buses are setup by default by kernel so tell mraa to ignore them
+    b->no_bus_mux = 1;
+    b->phy_pin_count = MRAA_RADXA_E25_PIN_COUNT + 1;
+
+    if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_E25)) {
+        b->platform_name = PLATFORM_NAME_RADXA_E25;
+    } else {
+        printf("An unknown product detected. Fail early...\n");
+        exit(-1);
+    }
+
+    b->chardev_capable = 1;
+
+    // UART
+    b->uart_dev_count = MRAA_RADXA_E25_UART_COUNT;
+    b->def_uart_dev = 0;
+    b->uart_dev[0].index = 3;
+    b->uart_dev[1].index = 5;
+    b->uart_dev[2].index = 7;
+    b->uart_dev[0].device_path = (char*) radxa_e25_serialdev[0];
+    b->uart_dev[1].device_path = (char*) radxa_e25_serialdev[1];
+    b->uart_dev[2].device_path = (char*) radxa_e25_serialdev[2];
+
+    // I2C
+    b->i2c_bus_count = MRAA_RADXA_E25_I2C_COUNT;
+    b->def_i2c_bus = 0;
+    b->i2c_bus[0].bus_id = 3;
+
+    // SPI
+    b->spi_bus_count = MRAA_RADXA_E25_SPI_COUNT;
+    b->def_spi_bus = 0;
+    b->spi_bus[0].bus_id = 0;
+    b->spi_bus[1].bus_id = 1;
+
+    // PWM
+    b->pwm_dev_count = MRAA_RADXA_E25_PWM_COUNT;
+    b->pwm_default_period = 500;
+    b->pwm_max_period = 2147483;
+    b->pwm_min_period = 1;
+
+    b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count);
+    if (b->pins == NULL) {
+        free(b->adv_func);
+        free(b);
+        return NULL;
+    }
+
+    b->pins[7].pwm.parent_id = 12;  // pwm12-m0
+    b->pins[7].pwm.mux_total = 0;
+    b->pins[11].pwm.parent_id = 14;  // pwm14-m0
+    b->pins[11].pwm.mux_total = 0;
+    b->pins[13].pwm.parent_id = 1; // pwm15-m0
+    b->pins[13].pwm.mux_total = 0;
+    b->pins[18].pwm.parent_id = 7; // pwm7-m0
+    b->pins[18].pwm.mux_total = 0;
+    b->pins[24].pwm.parent_id = 13; // pwm13-m1
+    b->pins[24].pwm.mux_total = 0;
+    b->pins[26].pwm.parent_id = 4;  // pwm13-m0
+    b->pins[26].pwm.mux_total = 0;
+
+    mraa_radxa_e25_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
+    mraa_radxa_e25_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3.3V");
+    mraa_radxa_e25_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5.0V");
+    mraa_radxa_e25_pininfo(b, 3, 1, 0, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO1_A0");
+    mraa_radxa_e25_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5.0V");
+    mraa_radxa_e25_pininfo(b, 5, 1, 1, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO1_A1");
+    mraa_radxa_e25_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
+    mraa_radxa_e25_pininfo(b, 7, 3, 15, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B7");
+    mraa_radxa_e25_pininfo(b, 8, 3, 18, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO3_C2");
+    mraa_radxa_e25_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
+    mraa_radxa_e25_pininfo(b, 10, 3, 19, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO3_C3");
+    mraa_radxa_e25_pininfo(b, 11, 3, 20, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C4");
+    mraa_radxa_e25_pininfo(b, 12, 3, 3, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A3");
+    mraa_radxa_e25_pininfo(b, 13, 3, 21, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C5");
+    mraa_radxa_e25_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
+    mraa_radxa_e25_pininfo(b, 15, 3, 17, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_C1");
+    mraa_radxa_e25_pininfo(b, 16, 2, 26, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO2_D2");
+    mraa_radxa_e25_pininfo(b, 17, 3, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_A1");
+    mraa_radxa_e25_pininfo(b, 18, 0, 22, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO0_C6");
+    mraa_radxa_e25_pininfo(b, 19, 2, 25, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO2_D1");
+    mraa_radxa_e25_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
+    mraa_radxa_e25_pininfo(b, 21, 2, 24, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO2_D0");
+    mraa_radxa_e25_pininfo(b, 22, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "SARADC_VIN5");
+    mraa_radxa_e25_pininfo(b, 23, 2, 27, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO2_D3");
+    mraa_radxa_e25_pininfo(b, 24, 4, 22, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO4_C6");
+    mraa_radxa_e25_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
+    mraa_radxa_e25_pininfo(b, 26, 3, 16, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C0");
+
+    return b;
+}