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10 changes: 9 additions & 1 deletion docs/features/baselibs/docs/architecture/index.rst
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Expand Up @@ -84,7 +84,15 @@ The decomposition of Baselibs into modular libraries is motivated by the need fo
Static Architecture
-------------------

.. feat_arc_sta:: Static View
.. feat:: Baselibs
:id: feat__baselibs
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__baselibs__json, logic_arc_int__baselibs__memory_shared, logic_arc_int__baselibs__message_passing, logic_arc_int__baselibs__result, logic_arc_int__baselibs__bit_manipulation, logic_arc_int__baselibs__bit_mask_operator, logic_arc_int__baselibs__dynamic_array, logic_arc_int__baselibs__intrusive_list, logic_arc_int__baselibs__filesystem, logic_arc_int__baselibs__utils_base64, logic_arc_int__baselibs__utils_scoped_op, logic_arc_int__baselibs__promise, logic_arc_int__baselibs__future, logic_arc_int__baselibs__shared_future, logic_arc_int__baselibs__executor, logic_arc_int__baselibs__task, logic_arc_int__baselibs__task_result, logic_arc_int__baselibs__synchronized_queue, logic_arc_int__baselibs__condition_variable
:consists_of: comp__com_configuration, comp__com_ipc_binding, comp__com_mock_binding, comp__com_frontend

.. feat_arc_sta:: Baselibs Static View
:id: feat_arc_sta__baselibs__static_view_arch
:security: YES
:safety: ASIL_B
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Expand Up @@ -30,8 +30,8 @@ see :need:`doc__bitmanipulation`
Static Architecture
-------------------

.. comp_arc_sta:: Bit Manipulation
:id: comp_arc_sta__baselibs__bit_manipulation
.. comp:: Bit Manipulation
:id: comp__baselibs_bit_manipulation
:security: NO
:safety: ASIL_B
:status: valid
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Expand Up @@ -30,8 +30,8 @@ see :need:`doc__concurrency`
Static Architecture
-------------------

.. comp_arc_sta:: Concurrency
:id: comp_arc_sta__baselibs__concurrency
.. comp:: Concurrency
:id: comp__baselibs_concurrency
:security: YES
:safety: ASIL_B
:status: valid
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Expand Up @@ -30,8 +30,8 @@ see :need:`doc__containers_architecture`
Static Architecture
-------------------

.. comp_arc_sta:: Containers
:id: comp_arc_sta__baselibs__containers
.. comp:: Containers
:id: comp__baselibs_containers
:security: YES
:safety: ASIL_B
:status: valid
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11 changes: 9 additions & 2 deletions docs/modules/baselibs/docs/index.rst
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Expand Up @@ -12,9 +12,16 @@
# SPDX-License-Identifier: Apache-2.0
# *******************************************************************************

.. mod_view_sta:: Baselibs
.. mod:: Baselibs
:id: mod__baselibs
:includes: comp__baselibs_json, comp__baselibs_message_passing, comp__baselibs_memory_shared, comp__baselibs_result, comp__baselibs_bit_manipulation, comp__baselibs_containers, comp__baselibs_filesystem, comp__baselibs_utils, comp__baselibs_concurrency
:status: valid
:safety: ASIL_B
:security: YES

.. mod_view_sta:: Baselibs Static View
:id: mod_view_sta__baselibs__baselibs
:includes: comp_arc_sta__baselibs__json, comp_arc_sta__baselibs__message_passing, comp_arc_sta__baselibs__memory_shared, comp_arc_sta__baselibs__result, comp_arc_sta__baselibs__bit_manipulation, comp_arc_sta__baselibs__containers, comp_arc_sta__baselibs__filesystem, comp_arc_sta__baselibs__utils, comp_arc_sta__baselibs__concurrency
:includes: comp__baselibs_json, comp__baselibs_message_passing, comp__baselibs_memory_shared, comp__baselibs_result, comp__baselibs_bit_manipulation, comp__baselibs_containers, comp__baselibs_filesystem, comp__baselibs_utils, comp__baselibs_concurrency

.. needarch::
:scale: 50
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Expand Up @@ -29,8 +29,8 @@ see :need:`doc__filesystem`
Static Architecture
-------------------

.. comp_arc_sta:: Filesystem
:id: comp_arc_sta__baselibs__filesystem
.. comp:: Filesystem
:id: comp__baselibs_filesystem
:security: YES
:safety: ASIL_B
:status: valid
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25 changes: 16 additions & 9 deletions docs/modules/baselibs/json/docs/architecture/index.rst
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Expand Up @@ -58,13 +58,21 @@ the main driver is to re-use existing implementation(s), enable switch of implem
Static Architecture
-------------------

.. comp_arc_sta:: JSON
:id: comp_arc_sta__baselibs__json
.. comp:: JSON
:id: comp__baselibs_json
:security: YES
:safety: ASIL_B
:status: valid
:implements: logic_arc_int__baselibs__json
:includes: comp_arc_sta__baselibs__json_wrapper, comp_arc_sta__baselibs__nlohman_json
:consists_of: comp__baselibs_json_wrapper, comp__baselibs_nlohman_json


.. comp_arc_sta:: JSON Static view
:id: comp_arc_sta__baselibs__json
:security: YES
:safety: ASIL_B
:status: valid
:includes: comp__baselibs_json_wrapper, comp__baselibs_nlohman_json
:fulfils: comp_req__json__deserialization, comp_req__json__serialization, comp_req__json__user_format, comp_req__json__lang_idioms, comp_req__json__lang_infra, comp_req__json__type_compatibility, comp_req__json__full_testability, comp_req__json__asil

.. needarch::
Expand Down Expand Up @@ -119,17 +127,16 @@ Interfaces
Lower Level Components
----------------------

.. comp_arc_sta:: JSON-Wrapper
:id: comp_arc_sta__baselibs__json_wrapper
.. comp:: JSON-Wrapper
:id: comp__baselibs_json_wrapper
:security: YES
:safety: ASIL_B
:status: valid
:implements: logic_arc_int__baselibs__json
:fulfils: comp_req__json__user_format, comp_req__json__lang_idioms, comp_req__json__lang_infra, comp_req__json__type_compatibility, comp_req__json__full_testability, comp_req__json__serialization, comp_req__json__asil

.. comp_arc_sta:: nlohman-JSON
:id: comp_arc_sta__baselibs__nlohman_json

.. comp:: nlohman-JSON
:id: comp__baselibs_nlohman_json
:security: YES
:safety: ASIL_B
:status: valid
:fulfils: comp_req__json__deserialization, comp_req__json__asil
Original file line number Diff line number Diff line change
Expand Up @@ -28,4 +28,4 @@ The component split was done nevertheless, because "JSON Wrapper" is implemented
"nlohman_json" is reused from open source.

So the requirements for "JSON Wrapper" are documented in :need:`doc__json_requirements`
(all requirements which are "fulfilled_by" :need:`comp_arc_sta__baselibs__json_wrapper`)
(all requirements which are "fulfilled_by" :need:`comp__baselibs_json_wrapper`)
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
Memory Shared Component Architecture
************************************

.. comp_arc_sta:: Memory Shared
:id: comp_arc_sta__baselibs__memory_shared
.. comp:: Memory Shared
:id: comp__baselibs_memory_shared
:security: YES
:safety: ASIL_B
:status: valid
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Expand Up @@ -15,8 +15,8 @@
Message Passing Component Architecture
**************************************

.. comp_arc_sta:: Message Passing
:id: comp_arc_sta__baselibs__message_passing
.. comp:: Message Passing
:id: comp__baselibs_message_passing
:security: YES
:safety: ASIL_B
:status: valid
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4 changes: 2 additions & 2 deletions docs/modules/baselibs/result/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -30,8 +30,8 @@ see :need:`doc__result`
Static Architecture
-------------------

.. comp_arc_sta:: Result
:id: comp_arc_sta__baselibs__result
.. comp:: Result
:id: comp__baselibs_result
:security: YES
:safety: ASIL_B
:status: valid
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Expand Up @@ -106,7 +106,7 @@ Requirement Inspection Checklist
- Does the requirement consider *external interfaces*?
- The SW platform's external interfaces (to the user) are defined in the Feature Architecture, so the Feature and Component Requirements should determine the input data use and setting of output data for these interfaces. Are all output values defined?
- YES
- Fixed: This could be improved by using the interfaces defined in :need:`comp_arc_sta__baselibs__result`
- Fixed: This could be improved by using the interfaces defined in :need:`comp__baselibs_result`
- `#2229 <https://github.com/eclipse-score/score/issues/2229>`_
* - REQ_07_01
- Is the *safety* attribute set correctly?
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4 changes: 2 additions & 2 deletions docs/modules/baselibs/utils/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ see :need:`doc__utils`
Static Architecture
-------------------

.. comp_arc_sta:: Utils
:id: comp_arc_sta__baselibs__utils
.. comp:: Utils
:id: comp__baselibs_utils
:security: YES
:safety: ASIL_B
:status: valid
Expand Down