Skip to content

Commit

Permalink
Merge pull request #4785 from janvrany/pr/riscv-instruction-printers
Browse files Browse the repository at this point in the history 
Implement instruction printers for RISC-V
  • Loading branch information
@0xdaryl
0xdaryl authored Jan 30, 2020
2 parents 82ecebb + 99dc4a0 commit bbf2a77
Show file tree
Hide file tree
Showing 6 changed files with 216 additions and 7 deletions.
3 changes: 2 additions & 1 deletion compiler/env/OMRCPU.hpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2019 IBM Corp. and others
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -128,6 +128,7 @@ class CPU
bool isPower() { return _majorArch == TR::arch_power; }
bool isARM() { return _majorArch == TR::arch_arm; }
bool isARM64() { return _majorArch == TR::arch_arm64; }
bool isRISCV() { return _majorArch == TR::arch_riscv; }

TR::MinorArchitecture minorArch() { return _minorArch; }
void setMinorArch(TR::MinorArchitecture a) { _minorArch = a; }
Expand Down
30 changes: 29 additions & 1 deletion compiler/ras/Debug.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2019 IBM Corp. and others
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -2803,6 +2803,14 @@ TR_Debug::print(TR::FILE *pOutFile, TR::Instruction * inst, const char *title)
}
#endif

#if defined(TR_TARGET_RISCV)
if (TR::Compiler->target.cpu.isRISCV())
{
print(pOutFile, inst);
return;
}
#endif

#if defined(TR_TARGET_S390)
if (_comp->target().cpu.isZ())
{
Expand Down Expand Up @@ -2859,6 +2867,14 @@ TR_Debug::print(TR::FILE *pOutFile, TR::GCRegisterMap * map)
}
#endif

#if defined(TR_TARGET_RISCV)
if (TR::Compiler->target.cpu.isRISCV())
{
printRVGCRegisterMap(pOutFile, map);
return;
}
#endif

}

void
Expand Down Expand Up @@ -3003,6 +3019,11 @@ TR_Debug::getName(TR::Register *reg, TR_RegisterSizes size)
if (_comp->target().cpu.isARM64())
return getName((TR::RealRegister *)reg, size);
#endif
#if defined(TR_TARGET_RISCV)
if (TR::Compiler->target.cpu.isRISCV())
return getName((TR::RealRegister *)reg, size);
#endif

TR_ASSERT(0, "TR_Debug::getName() ==> unknown target platform for given real register\n");
}

Expand Down Expand Up @@ -3183,6 +3204,13 @@ TR_Debug::print(TR::FILE *pOutFile, TR::Register * reg, TR_RegisterSizes size)
print(pOutFile, (TR::RealRegister *)reg, size);
return;
}
#endif
#if defined(TR_TARGET_RISCV)
if (TR::Compiler->target.cpu.isRISCV())
{
print(pOutFile, (TR::RealRegister *)reg, size);
return;
}
#endif
}
else
Expand Down
21 changes: 20 additions & 1 deletion compiler/ras/Debug.hpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2019 IBM Corp. and others
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -373,6 +373,16 @@ namespace TR { class ARM64UnresolvedCallSnippet; }
namespace TR { class ARM64VirtualUnresolvedSnippet; }
#endif


namespace TR { class RtypeInstruction; }
namespace TR { class ItypeInstruction; }
namespace TR { class StypeInstruction; }
namespace TR { class BtypeInstruction; }
namespace TR { class UtypeInstruction; }
namespace TR { class JtypeInstruction; }
namespace TR { class LoadInstruction; }
namespace TR { class StoreInstruction; }

TR_Debug *createDebugObject(TR::Compilation *);


Expand Down Expand Up @@ -1157,6 +1167,15 @@ class TR_Debug
void print(TR::FILE *, TR::LabelInstruction *);
void print(TR::FILE *, TR::AdminInstruction *);

void print(TR::FILE *, TR::RtypeInstruction *);
void print(TR::FILE *, TR::ItypeInstruction *);
void print(TR::FILE *, TR::StypeInstruction *);
void print(TR::FILE *, TR::BtypeInstruction *);
void print(TR::FILE *, TR::UtypeInstruction *);
void print(TR::FILE *, TR::JtypeInstruction *);
void print(TR::FILE *, TR::LoadInstruction * );
void print(TR::FILE *, TR::StoreInstruction *);

void print(TR::FILE *, TR::RealRegister *, TR_RegisterSizes size = TR_WordReg);
void print(TR::FILE *, TR::RegisterDependency *);
void print(TR::FILE *, TR::RegisterDependencyConditions *);
Expand Down
1 change: 1 addition & 0 deletions compiler/riscv/codegen/OMRInstruction.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,7 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
* @return description string
*/
virtual char *description() { return "RV"; }

/**
* @brief Gets instruction kind
* @return instruction kind
Expand Down
121 changes: 117 additions & 4 deletions compiler/riscv/codegen/RVDebug.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2019, 2019 IBM Corp. and others
* Copyright (c) 2019, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -72,6 +72,98 @@ TR_Debug::printMemoryReferenceComment(TR::FILE *pOutFile, TR::MemoryReference *m
print(pOutFile, mr->getSymbolReference());
}

void
TR_Debug::print(TR::FILE *pOutFile, TR::RtypeInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource1Register(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource2Register(), TR_WordReg);
trfflush(_comp->getOutFile());
}

void
TR_Debug::print(TR::FILE *pOutFile, TR::ItypeInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource1Register(), TR_WordReg);
trfprintf(pOutFile, ", 0x%04x (%d)", instr->getSourceImmediate(), instr->getSourceImmediate());
trfflush(_comp->getOutFile());
}

void
TR_Debug::print(TR::FILE *pOutFile, TR::StypeInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getSource1Register(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource2Register(), TR_WordReg);
trfprintf(pOutFile, ", 0x%04x (%d)", instr->getSourceImmediate(), instr->getSourceImmediate());
trfflush(_comp->getOutFile());
}
void

TR_Debug::print(TR::FILE *pOutFile, TR::BtypeInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getSource1Register(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource2Register(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getLabelSymbol());
trfflush(_comp->getOutFile());
}
void

TR_Debug::print(TR::FILE *pOutFile, TR::UtypeInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, ", 0x%08x (%d)", instr->getSourceImmediate(), instr->getSourceImmediate());
trfflush(_comp->getOutFile());
}
void

TR_Debug::print(TR::FILE *pOutFile, TR::JtypeInstruction *instr)
{
TR_Debug::print(pOutFile, (TR::UtypeInstruction*)instr);
//printPrefix(pOutFile, instr);
//trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
//trfflush(_comp->getOutFile());
}

void
TR_Debug::print(TR::FILE *pOutFile, TR::LoadInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, " <- ");
print(pOutFile, instr->getMemoryReference());
trfflush(_comp->getOutFile());
}

void
TR_Debug::print(TR::FILE *pOutFile, TR::StoreInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getSource1Register(), TR_WordReg);
trfprintf(pOutFile, " -> ");
print(pOutFile, instr->getMemoryReference());
trfflush(_comp->getOutFile());
}


void
TR_Debug::print(TR::FILE *pOutFile, TR::Instruction *instr)
{
Expand All @@ -86,10 +178,31 @@ TR_Debug::print(TR::FILE *pOutFile, TR::Instruction *instr)
case OMR::Instruction::IsAdmin:
print(pOutFile, (TR::AdminInstruction *)instr);
break;
case OMR::Instruction::IsRTYPE:
print(pOutFile, (TR::RtypeInstruction *)instr);
break;
case OMR::Instruction::IsITYPE:
print(pOutFile, (TR::ItypeInstruction *)instr);
break;
case OMR::Instruction::IsSTYPE:
print(pOutFile, (TR::StypeInstruction *)instr);
break;
case OMR::Instruction::IsBTYPE:
print(pOutFile, (TR::BtypeInstruction *)instr);
break;
case OMR::Instruction::IsUTYPE:
print(pOutFile, (TR::UtypeInstruction *)instr);
break;
case OMR::Instruction::IsJTYPE:
print(pOutFile, (TR::JtypeInstruction *)instr);
break;
case OMR::Instruction::IsLOAD:
print(pOutFile, (TR::LoadInstruction *)instr);
break;
case OMR::Instruction::IsSTORE:
print(pOutFile, (TR::StoreInstruction *)instr);
break;
default:
TR_ASSERT(false, "unexpected instruction kind");
// fall through
case OMR::Instruction::IsNotExtended:
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s", getOpCodeName(&instr->getOpCode()));
Expand Down
47 changes: 47 additions & 0 deletions compiler/riscv/codegen/RVInstruction.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,12 @@ class RtypeInstruction : public TR::Instruction
useRegister(s2reg);
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsRTYPE; }

/**
* @brief Gets target register
* @return target register
Expand Down Expand Up @@ -204,6 +210,12 @@ class ItypeInstruction : public TR::Instruction
useRegister(s1reg);
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsITYPE; }

/**
* @brief Gets target register
* @return target register
Expand Down Expand Up @@ -315,6 +327,12 @@ class LoadInstruction : public TR::Instruction
//mr->incRegisterTotalUseCounts(codeGen);
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsLOAD; }

/**
* @brief Gets target register
* @return target register
Expand Down Expand Up @@ -432,6 +450,12 @@ class StypeInstruction : public TR::Instruction
useRegister(s2reg);
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsSTYPE; }

/**
* @brief Gets source register 1
* @return source register
Expand Down Expand Up @@ -539,6 +563,12 @@ class StoreInstruction : public TR::Instruction
mr->bookKeepingRegisterUses(this, codeGen);
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsSTORE; }

/**
* @brief Gets source register
* @return source register
Expand Down Expand Up @@ -647,6 +677,12 @@ class BtypeInstruction : public StypeInstruction
{
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsBTYPE; }

uint32_t setSourceImmediate(uint32_t si)
{
TR_ASSERT(false, "Should not be used with B-type instructions, use setLabelSymbol()!");
Expand Down Expand Up @@ -734,6 +770,11 @@ class UtypeInstruction : public TR::Instruction
useRegister(treg);
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsUTYPE; }

/**
* @brief Gets target register
Expand Down Expand Up @@ -883,6 +924,12 @@ class JtypeInstruction : public UtypeInstruction
{
}

/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsJTYPE; }

/**
* @brief Gets label symbol
* @return label symbol
Expand Down

0 comments on commit bbf2a77

Please sign in to comment.