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Add recognition of modern Intel processors to port library and compiler
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* Cascade Lake
* Ice Lake
* Sapphire Rapids
* Emerald Rapids

Signed-off-by: Daryl Maier <maier@ca.ibm.com>
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@0xdaryl
0xdaryl committed Jun 1, 2024
1 parent 49be298 commit bbb2817
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Showing 6 changed files with 153 additions and 41 deletions.
40 changes: 22 additions & 18 deletions compiler/env/ProcessorInfo.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -243,27 +243,31 @@ inline uint32_t getFeatureFlags10Mask()

enum TR_ProcessorDescription
{
TR_ProcessorUnknown = 0x00000000,
TR_ProcessorIntelPentium = 0x00000001,
TR_ProcessorIntelP6 = 0x00000002,
TR_ProcessorIntelPentium4 = 0x00000003,
TR_ProcessorUnknown = 0x00000000,
TR_ProcessorIntelPentium = 0x00000001,
TR_ProcessorIntelP6 = 0x00000002,
TR_ProcessorIntelPentium4 = 0x00000003,

TR_ProcessorAMDK5 = 0x00000004,
TR_ProcessorAMDK6 = 0x00000005,
TR_ProcessorAMDAthlonDuron = 0x00000006,
TR_ProcessorAMDOpteron = 0x00000007,
TR_ProcessorAMDK5 = 0x00000004,
TR_ProcessorAMDK6 = 0x00000005,
TR_ProcessorAMDAthlonDuron = 0x00000006,
TR_ProcessorAMDOpteron = 0x00000007,

TR_ProcessorIntelCore2 = 0x00000008,
TR_ProcessorIntelTulsa = 0x00000009,
TR_ProcessorIntelNehalem = 0x0000000a,
TR_ProcessorIntelCore2 = 0x00000008,
TR_ProcessorIntelTulsa = 0x00000009,
TR_ProcessorIntelNehalem = 0x0000000a,

TR_ProcessorAMDFamily15h = 0x0000000b,
TR_ProcessorIntelWestmere = 0x0000000c,
TR_ProcessorIntelSandyBridge = 0x0000000d,
TR_ProcessorIntelIvyBridge = 0x0000000e,
TR_ProcessorIntelHaswell = 0x0000000f,
TR_ProcessorIntelBroadwell = 0x00000010,
TR_ProcessorIntelSkylake = 0x00000011,
TR_ProcessorAMDFamily15h = 0x0000000b,
TR_ProcessorIntelWestmere = 0x0000000c,
TR_ProcessorIntelSandyBridge = 0x0000000d,
TR_ProcessorIntelIvyBridge = 0x0000000e,
TR_ProcessorIntelHaswell = 0x0000000f,
TR_ProcessorIntelBroadwell = 0x00000010,
TR_ProcessorIntelSkylake = 0x00000011,
TR_ProcessorIntelCascadeLake = 0x00000012,
TR_ProcessorIntelIceLake = 0x00000013,
TR_ProcessorIntelSapphireRapids = 0x00000014,
TR_ProcessorIntelEmeraldRapids = 0x00000015,
};

#endif
23 changes: 22 additions & 1 deletion compiler/x/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -169,9 +169,30 @@ void TR_X86ProcessorInfo::initialize(bool force)
case 0x06:
{
uint32_t extended_model = getCPUModel(_processorSignature) + (getCPUExtendedModel(_processorSignature) << 4);
uint32_t processorStepping = getCPUStepping(_processorSignature);
switch (extended_model)
{
case 0x55:
case 0xcf:
_processorDescription |= TR_ProcessorIntelEmeraldRapids; break;
case 0x8f:
_processorDescription |= TR_ProcessorIntelSapphireRapids; break;
case 0x6a: // IceLake_X
case 0x6c: // IceLake_D
case 0x7d: // IceLake
case 0x7e: // IceLake_L
_processorDescription |= TR_ProcessorIntelIceLake; break;
case 0x55: // Skylake_X
if (processorStepping == 7)
{
_processorDescription |= TR_ProcessorIntelCascadeLake;
}
else
{
_processorDescription |= TR_ProcessorIntelSkylake;
}
break;
case 0x4e: // Skylake_L
case 0x5e: // Skylake
_processorDescription |= TR_ProcessorIntelSkylake; break;
case 0x4f:
_processorDescription |= TR_ProcessorIntelBroadwell; break;
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42 changes: 23 additions & 19 deletions compiler/x/codegen/OMRCodeGenerator.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -195,25 +195,29 @@ struct TR_X86ProcessorInfo
uint32_t getCPUExtendedModel(uint32_t signature) {return (signature & CPUID_SIGNATURE_EXTENDEDMODEL_MASK) >> 16;}
uint32_t getCPUExtendedFamily(uint32_t signature) {return (signature & CPUID_SIGNATURE_EXTENDEDFAMILY_MASK) >> 20;}

bool isIntelPentium() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelPentium; }
bool isIntelP6() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelP6; }
bool isIntelPentium4() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelPentium4; }
bool isIntelCore2() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelCore2; }
bool isIntelTulsa() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelTulsa; }
bool isIntelNehalem() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelNehalem; }
bool isIntelWestmere() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelWestmere; }
bool isIntelSandyBridge() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSandyBridge; }
bool isIntelIvyBridge() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelIvyBridge; }
bool isIntelHaswell() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelHaswell; }
bool isIntelBroadwell() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelBroadwell; }
bool isIntelSkylake() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSkylake; }

bool isIntelOldMachine() { return (isIntelPentium() || isIntelP6() || isIntelPentium4() || isIntelCore2() || isIntelTulsa() || isIntelNehalem()); }

bool isAMDK6() { return (_processorDescription & 0x000000fe) == TR_ProcessorAMDK5; } // accept either K5 or K6
bool isAMDAthlonDuron() { return (_processorDescription & 0x000000ff) == TR_ProcessorAMDAthlonDuron; }
bool isAMDOpteron() { return (_processorDescription & 0x000000ff) == TR_ProcessorAMDOpteron; }
bool isAMD15h() { return (_processorDescription & 0x000000ff) == TR_ProcessorAMDFamily15h; }
bool isIntelPentium() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelPentium; }
bool isIntelP6() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelP6; }
bool isIntelPentium4() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelPentium4; }
bool isIntelCore2() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelCore2; }
bool isIntelTulsa() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelTulsa; }
bool isIntelNehalem() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelNehalem; }
bool isIntelWestmere() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelWestmere; }
bool isIntelSandyBridge() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSandyBridge; }
bool isIntelIvyBridge() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelIvyBridge; }
bool isIntelHaswell() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelHaswell; }
bool isIntelBroadwell() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelBroadwell; }
bool isIntelSkylake() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSkylake; }
bool isIntelCascadeLake() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelCascadeLake; }
bool isIntelIceLake() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelIceLake; }
bool isIntelSapphireRapids() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSapphireRapids; }
bool isIntelEmeraldRapids() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelEmeraldRapids; }

bool isIntelOldMachine() { return (isIntelPentium() || isIntelP6() || isIntelPentium4() || isIntelCore2() || isIntelTulsa() || isIntelNehalem()); }

bool isAMDK6() { return (_processorDescription & 0x000000fe) == TR_ProcessorAMDK5; } // accept either K5 or K6
bool isAMDAthlonDuron() { return (_processorDescription & 0x000000ff) == TR_ProcessorAMDAthlonDuron; }
bool isAMDOpteron() { return (_processorDescription & 0x000000ff) == TR_ProcessorAMDOpteron; }
bool isAMD15h() { return (_processorDescription & 0x000000ff) == TR_ProcessorAMDFamily15h; }

bool isGenuineIntel() {return _vendorFlags.testAny(TR_GenuineIntel);}
bool isAuthenticAMD() {return _vendorFlags.testAny(TR_AuthenticAMD);}
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36 changes: 36 additions & 0 deletions compiler/x/env/OMRCPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -289,6 +289,14 @@ OMR::X86::CPU::is_test(OMRProcessorArchitecture p)
return TR::CodeGenerator::getX86ProcessorInfo().isIntelBroadwell() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTEL_SKYLAKE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelSkylake() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTEL_CASCADELAKE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelCascadeLake() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTEL_ICELAKE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelIceLake() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelSapphireRapids() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelEmeraldRapids() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_AMD_ATHLONDURON:
return TR::CodeGenerator::getX86ProcessorInfo().isAMDAthlonDuron() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_AMD_OPTERON:
Expand Down Expand Up @@ -455,6 +463,18 @@ OMR::X86::CPU::is_old_api(OMRProcessorArchitecture p)
case OMR_PROCESSOR_X86_INTEL_SKYLAKE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelSkylake();
break;
case OMR_PROCESSOR_X86_INTEL_CASCADELAKE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelCascadeLake();
break;
case OMR_PROCESSOR_X86_INTEL_ICELAKE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelIceLake();
break;
case OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelSapphireRapids();
break;
case OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelEmeraldRapids();
break;
case OMR_PROCESSOR_X86_AMD_ATHLONDURON:
ans = TR::CodeGenerator::getX86ProcessorInfo().isAMDAthlonDuron();
break;
Expand Down Expand Up @@ -685,6 +705,22 @@ OMR::X86::CPU::getProcessorName()
returnString = "X86 Intel Skylake";
break;

case OMR_PROCESSOR_X86_INTEL_CASCADELAKE:
returnString = "X86 Intel Cascade Lake";
break;

case OMR_PROCESSOR_X86_INTEL_ICELAKE:
returnString = "X86 Intel Ice Lake";
break;

case OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS:
returnString = "X86 Intel Sapphire Rapids";
break;

case OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS:
returnString = "X86 Intel Emerald Rapids";
break;

case OMR_PROCESSOR_X86_AMD_K5:
returnString = "X86 AMDK5";
break;
Expand Down
6 changes: 5 additions & 1 deletion include_core/omrport.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1465,7 +1465,11 @@ typedef enum OMRProcessorArchitecture {
OMR_PROCESSOR_X86_INTEL_HASWELL,
OMR_PROCESSOR_X86_INTEL_BROADWELL,
OMR_PROCESSOR_X86_INTEL_SKYLAKE,
OMR_PROCESSOR_X86_INTEL_LAST = OMR_PROCESSOR_X86_INTEL_SKYLAKE,
OMR_PROCESSOR_X86_INTEL_CASCADELAKE,
OMR_PROCESSOR_X86_INTEL_ICELAKE,
OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS,
OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS,
OMR_PROCESSOR_X86_INTEL_LAST = OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS,
OMR_PROCESSOR_X86_AMD_FIRST,
OMR_PROCESSOR_X86_AMD_K5 = OMR_PROCESSOR_X86_AMD_FIRST,
OMR_PROCESSOR_X86_AMD_K6,
Expand Down
47 changes: 45 additions & 2 deletions port/common/omrsysinfo_helpers.c
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,27 @@
#define CPUID_FAMILYCODE_INTEL_CORE 0x06
#define CPUID_FAMILYCODE_INTEL_PENTIUM4 0x0F

#define CPUID_MODELCODE_INTEL_SKYLAKE 0x55
/**
* Intel model code suffix naming convention (post-Broadwell)
*
* _X : server part (Xeon)
* _D : micro server
* _L : mobile
* : client
*/
#define CPUID_MODELCODE_INTEL_EMERALDRAPIDS_X 0xCF

#define CPUID_MODELCODE_INTEL_SAPPHIRERAPIDS_X 0x8F

#define CPUID_MODELCODE_INTEL_ICELAKE_X 0x6A
#define CPUID_MODELCODE_INTEL_ICELAKE_D 0x6C
#define CPUID_MODELCODE_INTEL_ICELAKE 0x7D
#define CPUID_MODELCODE_INTEL_ICELAKE_L 0x7E

#define CPUID_MODELCODE_INTEL_SKYLAKE_L 0x4E
#define CPUID_MODELCODE_INTEL_SKYLAKE 0x5E
#define CPUID_MODELCODE_INTEL_SKYLAKE_X 0x55

#define CPUID_MODELCODE_INTEL_BROADWELL 0x4F
#define CPUID_MODELCODE_INTEL_HASWELL_1 0x3F
#define CPUID_MODELCODE_INTEL_HASWELL_2 0x3C
Expand All @@ -84,6 +104,8 @@
#define CPUID_MODELCODE_INTEL_CORE2_HARPERTOWN 0x17
#define CPUID_MODELCODE_INTEL_CORE2_WOODCREST_CLOVERTOWN 0x0F

#define CPUID_STEPPING_INTEL_CASCADELAKE 0x07

#define CPUID_FAMILYCODE_AMD_KSERIES 0x05
#define CPUID_FAMILYCODE_AMD_ATHLON 0x06
#define CPUID_FAMILYCODE_AMD_OPTERON 0x0F
Expand Down Expand Up @@ -247,6 +269,7 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD
char vendor[12];
uint32_t familyCode = 0;
uint32_t processorSignature = 0;
uint32_t processorStepping = 0;

desc->processor = OMR_PROCESSOR_X86_UNKNOWN;

Expand All @@ -260,6 +283,7 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD
omrsysinfo_get_x86_cpuid(CPUID_FAMILY_INFO, CPUInfo);
processorSignature = CPUInfo[CPUID_EAX];
familyCode = (processorSignature & CPUID_SIGNATURE_FAMILY) >> CPUID_SIGNATURE_FAMILY_SHIFT;
processorStepping = (processorSignature & CPUID_SIGNATURE_STEPPING) >> CPUID_SIGNATURE_STEPPING_SHIFT;
if (0 == strncmp(vendor, CPUID_VENDOR_INTEL, CPUID_VENDOR_LENGTH)) {
switch (familyCode) {
case CPUID_FAMILYCODE_INTEL_PENTIUM:
Expand All @@ -272,8 +296,27 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD
uint32_t totalModelCode = modelCode + (extendedModelCode << 4);

switch (totalModelCode) {
case CPUID_MODELCODE_INTEL_EMERALDRAPIDS_X:
desc->processor = OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS;
break;
case CPUID_MODELCODE_INTEL_SAPPHIRERAPIDS_X:
desc->processor = OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS;
break;
case CPUID_MODELCODE_INTEL_ICELAKE_X:
case CPUID_MODELCODE_INTEL_ICELAKE_D:
case CPUID_MODELCODE_INTEL_ICELAKE_L:
case CPUID_MODELCODE_INTEL_ICELAKE:
desc->processor = OMR_PROCESSOR_X86_INTEL_ICELAKE;
break;
case CPUID_MODELCODE_INTEL_SKYLAKE_X:
case CPUID_MODELCODE_INTEL_SKYLAKE_L:
case CPUID_MODELCODE_INTEL_SKYLAKE:
desc->processor = OMR_PROCESSOR_X86_INTEL_SKYLAKE;
if (CPUID_STEPPING_INTEL_CASCADELAKE == processorStepping) {
desc->processor = OMR_PROCESSOR_X86_INTEL_CASCADELAKE;
}
else {
desc->processor = OMR_PROCESSOR_X86_INTEL_SKYLAKE;
}
break;
case CPUID_MODELCODE_INTEL_BROADWELL:
desc->processor = OMR_PROCESSOR_X86_INTEL_BROADWELL;
Expand Down

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