Merge pull request #4722 from Akira1Saitoh/aarch64GenerateNop

AArch64: Add generateNop to code generator
eclipse-openj9 · Jan 16, 2020 · 8a8b562 · 8a8b562
2 parents 2bcc2ad + a32deed
commit 8a8b562
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Showing 2 changed files with 18 additions and 2 deletions.
diff --git a/compiler/aarch64/codegen/OMRCodeGenerator.cpp b/compiler/aarch64/codegen/OMRCodeGenerator.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2018, 2019 IBM Corp. and others
+ * Copyright (c) 2018, 2020 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -534,3 +534,12 @@ OMR::ARM64::CodeGenerator::directCallRequiresTrampoline(intptrj_t targetAddress,
       !self()->comp()->target().cpu.isTargetWithinUnconditionalBranchImmediateRange(targetAddress, sourceAddress) ||
       self()->comp()->getOption(TR_StressTrampolines);
    }
+
+TR::Instruction *
+OMR::ARM64::CodeGenerator::generateNop(TR::Node *node, TR::Instruction *preced)
+   {
+   if (preced)
+      return new (self()->trHeapMemory()) TR::Instruction(TR::InstOpCode::nop, node, preced, self());
+   else
+      return new (self()->trHeapMemory()) TR::Instruction(TR::InstOpCode::nop, node, self());
+   }
diff --git a/compiler/aarch64/codegen/OMRCodeGenerator.hpp b/compiler/aarch64/codegen/OMRCodeGenerator.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2018, 2019 IBM Corp. and others
+ * Copyright (c) 2018, 2020 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -393,6 +393,13 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
     */
    void generateBinaryEncodingPrePrologue(TR_ARM64BinaryEncodingData &data);
 
+   /**
+    * @brief Generates nop
+    * @param[in] node: node
+    * @param[in] preced : preceding instruction
+    */
+   TR::Instruction *generateNop(TR::Node *node, TR::Instruction *preced = 0);
+
    private:
 
    enum // flags