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Merge pull request #4514 from simonameng/x86DsqrtEvaluator
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Adding `dsqrtEvaluator` on X86
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andrewcraik authored Nov 20, 2019
2 parents 9747d58 + 48d13f2 commit 1e4b624
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Showing 5 changed files with 23 additions and 1 deletion.
2 changes: 1 addition & 1 deletion compiler/x/amd64/codegen/OMRTreeEvaluatorTable.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -708,7 +708,7 @@
TR::TreeEvaluator::unImpOpEvaluator, // TR::fnint
TR::TreeEvaluator::unImpOpEvaluator, // TR::dnint
TR::TreeEvaluator::fpSqrtEvaluator, // TR::fsqrt
TR::TreeEvaluator::fpSqrtEvaluator, // TR::dsqrt
TR::TreeEvaluator::dsqrtEvaluator, // TR::dsqrt
TR::TreeEvaluator::unImpOpEvaluator, // TR::getstack
TR::TreeEvaluator::unImpOpEvaluator, // TR::dealloca
TR::TreeEvaluator::unImpOpEvaluator, // TR::idoz
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13 changes: 13 additions & 0 deletions compiler/x/codegen/FPTreeEvaluator.cpp
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Expand Up @@ -722,6 +722,19 @@ TR::Register *OMR::X86::TreeEvaluator::fpSqrtEvaluator(TR::Node *node, TR::CodeG
return result;
}

TR::Register *OMR::X86::TreeEvaluator::dsqrtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *operand = node->getFirstChild();
TR::Register *opRegister = cg->evaluate(operand);
TR::Register *targetRegister = cg->allocateRegister(TR_FPR);

generateRegRegInstruction(SQRTSDRegReg, node, targetRegister, opRegister, cg);

node->setRegister(targetRegister);
cg->decReferenceCount(operand);
return targetRegister;
}

TR::Register *OMR::X86::TreeEvaluator::faddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, true, cg);
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1 change: 1 addition & 0 deletions compiler/x/codegen/OMRTreeEvaluator.hpp
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Expand Up @@ -279,6 +279,7 @@ class OMR_EXTENSIBLE TreeEvaluator: public OMR::TreeEvaluator
static TR::Register *fpReturnEvaluator(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *fpRemEvaluator(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *fpSqrtEvaluator(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *dsqrtEvaluator(TR::Node *node, TR::CodeGenerator *cg);

// routines for floating point values that can fit in one GPR
static TR::Register *floatingPointStoreEvaluator(TR::Node *node, TR::CodeGenerator *cg);
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6 changes: 6 additions & 0 deletions compiler/x/env/OMRCPU.cpp
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Expand Up @@ -108,6 +108,12 @@ OMR::X86::CPU::getX86ProcessorFeatureFlags8()
return self()->queryX86TargetCPUID()->_featureFlags8;
}

bool
OMR::X86::CPU::getSupportsHardwareSQRT()
{
return true;
}

bool
OMR::X86::CPU::testOSForSSESupport()
{
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2 changes: 2 additions & 0 deletions compiler/x/env/OMRCPU.hpp
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Expand Up @@ -62,6 +62,8 @@ class CPU : public OMR::CPU
uint32_t getX86ProcessorFeatureFlags2();
uint32_t getX86ProcessorFeatureFlags8();

bool getSupportsHardwareSQRT();

bool testOSForSSESupport();


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