Merge pull request #5290 from knn-k/aarch64instr38

AArch64: Implement insertZeroRegister() in some Instruction classes
eclipse-omr · Jun 6, 2020 · 36e663b · 36e663b
2 parents 4248a08 + da81fde
commit 36e663b
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Showing 3 changed files with 38 additions and 28 deletions.
diff --git a/compiler/aarch64/codegen/ARM64BinaryEncoding.cpp b/compiler/aarch64/codegen/ARM64BinaryEncoding.cpp
@@ -460,11 +460,10 @@ uint8_t *TR::ARM64Trg1ZeroSrc1Instruction::generateBinaryEncoding()
    {
    uint8_t *instructionStart = cg()->getBinaryBufferCursor();
    uint8_t *cursor = instructionStart;
-   TR::RealRegister *zeroReg = cg()->machine()->getRealRegister(TR::RealRegister::xzr);
    cursor = getOpCode().copyBinaryToBuffer(instructionStart);
    insertTargetRegister(toARM64Cursor(cursor));
    insertSource1Register(toARM64Cursor(cursor));
-   zeroReg->setRegisterFieldRN(toARM64Cursor(cursor));
+   insertZeroRegister(toARM64Cursor(cursor));
    cursor += ARM64_INSTRUCTION_LENGTH;
    setBinaryLength(ARM64_INSTRUCTION_LENGTH);
    setBinaryEncoding(instructionStart);
@@ -490,10 +489,8 @@ uint8_t *TR::ARM64ZeroSrc1ImmInstruction::generateBinaryEncoding()
    {
    uint8_t *instructionStart = cg()->getBinaryBufferCursor();
    uint8_t *cursor = instructionStart;
-   TR::RealRegister *zeroReg = cg()->machine()->getRealRegister(TR::RealRegister::xzr);
-
    cursor = getOpCode().copyBinaryToBuffer(instructionStart);
-   zeroReg->setRegisterFieldRD(toARM64Cursor(cursor));
+   insertZeroRegister(toARM64Cursor(cursor));
    insertSource1Register(toARM64Cursor(cursor));
    insertImmediateField(toARM64Cursor(cursor));
    insertNbit(toARM64Cursor(cursor));
@@ -717,10 +714,8 @@ uint8_t *TR::ARM64ZeroSrc2Instruction::generateBinaryEncoding()
    {
    uint8_t *instructionStart = cg()->getBinaryBufferCursor();
    uint8_t *cursor = instructionStart;
-   TR::RealRegister *zeroReg = cg()->machine()->getRealRegister(TR::RealRegister::xzr);
-
    cursor = getOpCode().copyBinaryToBuffer(instructionStart);
-   zeroReg->setRegisterFieldRD(toARM64Cursor(cursor));
+   insertZeroRegister(toARM64Cursor(cursor));
    insertSource1Register(toARM64Cursor(cursor));
    insertSource2Register(toARM64Cursor(cursor));
    cursor += ARM64_INSTRUCTION_LENGTH;

diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -1203,23 +1203,8 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1Src2Instruction *instr)
    {
    printPrefix(pOutFile, instr);
    TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
-   bool isCmp = false;
-   if (op == TR::InstOpCode::subsx || op == TR::InstOpCode::subsw)
-      {
-      TR::Register *r = instr->getTargetRegister();
-      if (r && r->getRealRegister()
-          && toRealRegister(r)->getRegisterNumber() == TR::RealRegister::xzr)
-         {
-         // cmp alias
-         isCmp = true;
-         trfprintf(pOutFile, "cmp%c \t", (op == TR::InstOpCode::subsx) ? 'x' : 'w');
-         }
-      }
-   if (!isCmp)
-      {
-      trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
-      print(pOutFile, instr->getTargetRegister(), TR_WordReg); trfprintf(pOutFile, ", ");
-      }
+   trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
+   print(pOutFile, instr->getTargetRegister(), TR_WordReg); trfprintf(pOutFile, ", ");
    print(pOutFile, instr->getSource1Register(), TR_WordReg); trfprintf(pOutFile, ", ");
    print(pOutFile, instr->getSource2Register(), TR_WordReg);
 

diff --git a/compiler/aarch64/codegen/ARM64Instruction.hpp b/compiler/aarch64/codegen/ARM64Instruction.hpp
@@ -1578,7 +1578,7 @@ class ARM64Trg1Src1Instruction : public ARM64Trg1Instruction
 
 /*
  * This class is designated to be used for alias instruction such as movw, movx, negw, negx
- */ 
+ */
 class ARM64Trg1ZeroSrc1Instruction : public ARM64Trg1Src1Instruction
    {
    public:
@@ -1629,6 +1629,16 @@ class ARM64Trg1ZeroSrc1Instruction : public ARM64Trg1Src1Instruction
       source1->setRegisterFieldRM(instruction);
       }
 
+   /**
+    * @brief Sets zero register in binary encoding
+    * @param[in] instruction : instruction cursor
+    */
+   void insertZeroRegister(uint32_t *instruction)
+      {
+      TR::RealRegister *zeroReg = cg()->machine()->getRealRegister(TR::RealRegister::xzr);
+      zeroReg->setRegisterFieldRN(instruction);
+      }
+
    /**
     * @brief Generates binary encoding of the instruction
     * @return instruction cursor
@@ -3240,7 +3250,7 @@ class ARM64Src1Instruction : public TR::Instruction
 
 /*
  * This class is designated to be used for alias instruction such as cmpimmw, cmpimmx, tstimmw, tstimmx
- */ 
+ */
 class ARM64ZeroSrc1ImmInstruction : public ARM64Src1Instruction
    {
    uint32_t _source1Immediate;
@@ -3337,9 +3347,19 @@ class ARM64ZeroSrc1ImmInstruction : public ARM64Src1Instruction
     * @brief Sets the N bit (bit 22)
     * @param[in] n : N bit value
     * @return N bit value
-    */ 
+    */
    bool setNbit(bool n) { return (_Nbit = n);}
 
+   /**
+    * @brief Sets zero register in binary encoding
+    * @param[in] instruction : instruction cursor
+    */
+   void insertZeroRegister(uint32_t *instruction)
+      {
+      TR::RealRegister *zeroReg = cg()->machine()->getRealRegister(TR::RealRegister::xzr);
+      zeroReg->setRegisterFieldRD(instruction);
+      }
+
    /**
     * @brief Sets immediate field in binary encoding
     * @param[in] instruction : instruction cursor
@@ -3531,6 +3551,16 @@ class ARM64ZeroSrc2Instruction : public ARM64Src2Instruction
     */
    virtual Kind getKind() { return IsZeroSrc2; }
 
+   /**
+    * @brief Sets zero register in binary encoding
+    * @param[in] instruction : instruction cursor
+    */
+   void insertZeroRegister(uint32_t *instruction)
+      {
+      TR::RealRegister *zeroReg = cg()->machine()->getRealRegister(TR::RealRegister::xzr);
+      zeroReg->setRegisterFieldRD(instruction);
+      }
+
    /**
     * @brief Generates binary encoding of the instruction
     * @return instruction cursor