Merge pull request #5263 from knn-k/aarch64cmnimm

AArch64: Allow negative constant for generateCompareImmInstruction()
eclipse-omr · Jun 2, 2020 · 16d5a51 · 16d5a51
2 parents 2ad3c23 + 3504807
commit 16d5a51
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Showing 3 changed files with 44 additions and 7 deletions.
diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -916,15 +916,31 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1Src1ImmInstruction *instr)
    printPrefix(pOutFile, instr);
    TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
    bool done = false;
-   if (op == TR::InstOpCode::subsimmx || op == TR::InstOpCode::subsimmw)
+   if (op == TR::InstOpCode::subsimmx || op == TR::InstOpCode::subsimmw ||
+       op == TR::InstOpCode::addsimmx || op == TR::InstOpCode::addsimmw)
       {
       TR::Register *r = instr->getTargetRegister();
       if (r && r->getRealRegister()
           && toRealRegister(r)->getRegisterNumber() == TR::RealRegister::xzr)
          {
-         // cmp alias
+         // cmp/cmn alias
+         char *mnemonic = NULL;
          done = true;
-         trfprintf(pOutFile, "cmpimm%c \t", (op == TR::InstOpCode::subsimmx) ? 'x' : 'w');
+         switch (op)
+            {
+            case TR::InstOpCode::subsimmx:
+               mnemonic = "cmpimmx";
+               break;
+            case TR::InstOpCode::subsimmw:
+               mnemonic = "cmpimmw";
+               break;
+            case TR::InstOpCode::addsimmx:
+               mnemonic = "cmnimmx";
+               break;
+            case TR::InstOpCode::addsimmw:
+               mnemonic = "cmnimmw";
+            }
+         trfprintf(pOutFile, "%s \t", mnemonic);
          print(pOutFile, instr->getSource1Register(), TR_WordReg);
          trfprintf(pOutFile, ", %d", instr->getSourceImmediate());
          }

diff --git a/compiler/aarch64/codegen/ControlFlowEvaluator.cpp b/compiler/aarch64/codegen/ControlFlowEvaluator.cpp
@@ -136,6 +136,11 @@ if (cg->profiledPointersRequireRelocation() && secondChild->getOpCodeValue() ==
          generateCompareImmInstruction(cg, node, src1Reg, value, is64bit);
          useRegCompare = false;
          }
+      else if (constantIsUnsignedImm12(-value))
+         {
+         generateCompareImmInstruction(cg, node, src1Reg, value, is64bit);
+         useRegCompare = false;
+         }
       }
 
    if (useRegCompare)
@@ -332,6 +337,11 @@ static TR::Register *icmpHelper(TR::Node *node, TR::ARM64ConditionCode cc, bool
          generateCompareImmInstruction(cg, node, src1Reg, value, is64bit);
          useRegCompare = false;
          }
+      else if (constantIsUnsignedImm12(-value))
+         {
+         generateCompareImmInstruction(cg, node, src1Reg, value, is64bit);
+         useRegCompare = false;
+         }
       }
 
    if (useRegCompare)

diff --git a/compiler/aarch64/codegen/GenerateInstructions.cpp b/compiler/aarch64/codegen/GenerateInstructions.cpp
@@ -372,10 +372,21 @@ static TR::Instruction *generateZeroSrc1ImmInstruction(TR::CodeGenerator *cg, TR
 TR::Instruction *generateCompareImmInstruction(TR::CodeGenerator *cg, TR::Node *node,
    TR::Register *sreg, int32_t imm, bool is64bit, TR::Instruction *preced)
    {
-   /* Alias of SUBS instruction */
-
-   TR::InstOpCode::Mnemonic op = is64bit ? TR::InstOpCode::subsimmx : TR::InstOpCode::subsimmw;
-   TR_ASSERT_FATAL(constantIsUnsignedImm12(imm), "Immediate value is out of range for subsimm");
+   TR::InstOpCode::Mnemonic op;
+
+   if (constantIsUnsignedImm12(imm))
+      {
+      /* Alias of SUBS instruction */
+      op = is64bit ? TR::InstOpCode::subsimmx : TR::InstOpCode::subsimmw;
+      }
+   else
+      {
+      TR_ASSERT_FATAL(constantIsUnsignedImm12(-imm), "Immediate value is out of range for cmp/cmn");
+
+      /* Alias of ADDS instruction */
+      op = is64bit ? TR::InstOpCode::addsimmx : TR::InstOpCode::addsimmw;
+      imm = -imm;
+      }
 
    return generateZeroSrc1ImmInstruction(cg, op, node, sreg, imm, preced);
    }