Skip to content
View duyhieubui's full-sized avatar

Block or report duyhieubui

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. caravel_vco_adc caravel_vco_adc Public

    Forked from efabless/caravel_user_project

    https://caravel-user-project.readthedocs.io

    Verilog 7 2

  2. bsg_manycore bsg_manycore Public

    Forked from bespoke-silicon-group/bsg_manycore

    Tile based architecture designed for computing efficiency, scalability and generality

    Verilog

  3. basejump_stl basejump_stl Public

    Forked from bespoke-silicon-group/basejump_stl

    BaseJump STL: A Standard Template Library for SystemVerilog

    Verilog

  4. arty_pulpino arty_pulpino Public

    Forked from quangdaovu/arty_pulpino

    PULPino port that works as standalone version on Arty board.

    Verilog

  5. pulpino pulpino Public

    Forked from pulp-platform/pulpino

    An open-source microcontroller system based on RISC-V

    C

  6. debug_bridge debug_bridge Public

    Forked from pulp-platform/debug_bridge

    C++