Learning FPGA, yosys, nextpnr, and RISC-V

CUDA on non-NVIDIA GPUs

a model of MIR and the Rust type/trait system

A firewall that utilizes the Linux kernel's XDP hook. The XDP hook allows for very fast network processing on Linux systems. This is great for dropping malicious traffic from a (D)DoS attack. IPv6 …

Empowering everyone to build reliable and efficient software.

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

MATLAB implementation of a transmitter and receiver chain of the 5G NR Physical Uplink Shared Channel (PUSCH) defined by 3GPP rel 15.

A Library of Chisel3 Tools for Digital Signal Processing

This project contains generic example hardware modules and their testbenches written in Chisel and cocotb to demonstrate an agile hardware development methodology.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

rFaaS: a high-performance FaaS platform with RDMA acceleration for low-latency invocations.

Digital Communication with Python

An open-source library for Python 3 providing tools for analysis and simulation of analog and digital communication systems.

A rust drawing library for high quality data plotting for both WASM and native, statically and realtimely 🦀 📈🚀

Formal verification tool for Rust: check 100% of execution cases of your programs 🦀 to make applications with no bugs! ✈️ 🚀 ⚕️ 🏦

TorchSig is an open-source signal processing machine learning toolkit based on the PyTorch data handling pipeline.

A Linux kernel module that implements the Homa transport protocol.

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Advanced examples of Linux Device Drivers (LDD3) and detailed manual for running examples in QEMU which is patched with virtual PCI, USB, serial devices. I am actively composing a new book about Dr…

Reed Solomon (RS) decoder using Modified Euclidean algorithm parallel architecture

LLM training in simple, raw C/CUDA

A correct C89/C90/C99/C11/C18 parser written using Menhir and OCaml

Implementation of CNN using Verilog

Research and Materials on Hardware implementation of Transformer Model

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.