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add self-corrected algorithm and remade vertical step flow control
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@dshekhalev
dshekhalev committed Feb 4, 2023
1 parent ebb9a87 commit c3f347b
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Showing 4 changed files with 112 additions and 43 deletions.
5 changes: 2 additions & 3 deletions rtl/ldpc_dvb/dec/ldpc_dvb_dec_2d_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -302,12 +302,10 @@ module ldpc_dvb_dec_2d_ctrl
if (state == cWAIT_STATE) begin
oload_mode <= 1'b1;
end
else if (state == cWAIT_HDONE_STATE & !icnode_busy) begin
else if (state == cWAIT_VDONE_STATE & !ivnode_busy) begin
oload_mode <= 1'b0;
end
//
oc_nv_mode <= (state == cHSTEP_STATE) | (state == cWAIT_HDONE_STATE);
//
olast_iter <= ((state == cVSTEP_STATE) | (state == cWAIT_VDONE_STATE)) & do_last;
end
end
Expand All @@ -316,6 +314,7 @@ module ldpc_dvb_dec_2d_ctrl

assign ocycle_start = ((state == cVSTEP_STATE) | (state == cHSTEP_STATE)) & cycle_cnt.zero;
assign ocycle_read = (state == cVSTEP_STATE) | (state == cHSTEP_STATE);
assign oc_nv_mode = (state == cHSTEP_STATE) | (state == cWAIT_HDONE_STATE);

assign ocycle_strb.sof = cycle_cnt.zero;
assign ocycle_strb.sop = '0;
Expand Down
25 changes: 13 additions & 12 deletions rtl/ldpc_dvb/dec/ldpc_dvb_dec_2d_engine.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,8 @@
//
parameter bit pCODEGR = 1 ;
//
parameter int pCNORM_FACTOR = 6 ;
parameter int pNORM_FACTOR = 7 ;
parameter int pNORM_OFFSET = 1 ;
//
parameter bit pDO_LLR_INVERSION = 1 ;
parameter bit pUSE_SRL_FIFO = 1 ;
Expand Down Expand Up @@ -68,7 +69,8 @@
.pERR_W ( pERR_W ) ,
//
.pCODEGR ( pCODEGR ) ,
.pCNORM_FACTOR ( pCNORM_FACTOR ) ,
.pNORM_FACTOR ( pNORM_FACTOR ) ,
.pNORM_OFFSET ( pNORM_OFFSET ) ,
//
.pDO_LLR_INVERSION ( pDO_LLR_INVERSION ) ,
.pUSE_SRL_FIFO ( pUSE_SRL_FIFO ) ,
Expand Down Expand Up @@ -172,8 +174,6 @@ module ldpc_dvb_dec_2d_engine
//
parameter int pERR_W = 16 ;
//
parameter int pCNORM_FACTOR = 7 ; // horizontal step normalization factor

parameter bit pDO_LLR_INVERSION = 1 ; // do metric inversion inside decoder

parameter bit pUSE_SRL_FIFO = 1 ; // use SRL based internal FIFO
Expand Down Expand Up @@ -226,7 +226,7 @@ module ldpc_dvb_dec_2d_engine
localparam int cNODE_RAM_DAT_W = pNODE_W * cZC_MAX;

localparam int cSTATE_RAM_ADDR_W = cNODE_RAM_ADDR_W ;
localparam int cSTATE_RAM_DAT_W = (1 + (pUSE_SC_MODE ? $bits(node_state_t) : 0)) * cZC_MAX; // +1 for syndrome decision
localparam int cSTATE_RAM_DAT_W = (1 + (pUSE_SC_MODE ? cNODE_STATE_W : 0)) * cZC_MAX; // +1 for syndrome decision

//------------------------------------------------------------------------------------------------------
//
Expand Down Expand Up @@ -624,8 +624,8 @@ module ldpc_dvb_dec_2d_engine
if (pUSE_SC_MODE) begin
state_ram__iwdat[cSTATE_RAM_DAT_W-1 -: cZC_MAX] <= vnode__ovnode_hd;
//
for (int z = 0; z < cZC_MAX; z++) begin
state_ram__iwdat[z*cNODE_STATE_W +: cNODE_STATE_W] <= vnode__ovnode_state[z];
for (int i = 0; i < cZC_MAX; i++) begin
state_ram__iwdat[i*cNODE_STATE_W +: cNODE_STATE_W] <= vnode__ovnode_state[i];
end
end
else begin
Expand All @@ -638,8 +638,8 @@ module ldpc_dvb_dec_2d_engine
if (pUSE_SC_MODE) begin
state_ram_rdat_hd = state_ram__ordat[cSTATE_RAM_DAT_W-1 -: cZC_MAX];
//
for (int z = 0; z < cZC_MAX; z++) begin
state_ram_rdat_node_state[z] = state_ram__ordat[z*cNODE_STATE_W +: cNODE_STATE_W];
for (int i = 0; i < cZC_MAX; i++) begin
state_ram_rdat_node_state[i] = state_ram__ordat[i*cNODE_STATE_W +: cNODE_STATE_W];
end
end
else begin
Expand All @@ -657,7 +657,8 @@ module ldpc_dvb_dec_2d_engine
.pLLR_W ( pLLR_W ) ,
.pNODE_W ( pNODE_W ) ,
//
.pNORM_FACTOR ( pCNORM_FACTOR ) ,
.pNORM_FACTOR ( pNORM_FACTOR ) ,
.pNORM_OFFSET ( pNORM_OFFSET ) ,
//
.pUSE_SRL_FIFO ( pUSE_SRL_FIFO )
)
Expand Down Expand Up @@ -685,7 +686,7 @@ module ldpc_dvb_dec_2d_engine
.obusy ( cnode__obusy )
);

assign cnode__istart = ctrl__ocycle_start;// & ctrl__oc_nv_mode;
assign cnode__istart = ctrl__ocycle_start & ctrl__oc_nv_mode;
assign cnode__iload_iter = ctrl__oload_mode;

assign cnode__ival = rdat_val [cRDAT_DELAY-1] & ctrl__oc_nv_mode;
Expand Down Expand Up @@ -742,7 +743,7 @@ module ldpc_dvb_dec_2d_engine
.obusy ( vnode__obusy )
);

assign vnode__istart = ctrl__ocycle_start;// & !ctrl__oc_nv_mode;
assign vnode__istart = ctrl__ocycle_start & !ctrl__oc_nv_mode;
assign vnode__iload_iter = ctrl__oload_mode;

assign vnode__ival = rdat_val [cRDAT_DELAY-1] & !ctrl__oc_nv_mode;
Expand Down
59 changes: 39 additions & 20 deletions rtl/ldpc_dvb/dec/ldpc_dvb_dec_vnode.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,6 @@
parameter int pLLR_W = 4 ;
parameter int pNODE_W = 8 ;
//
parameter int pNORM_FACTOR = 6 ;
//
parameter int pUSE_SC_MODE = 1 ;
parameter bit pDO_LLR_INVERSION = 0 ;
parameter bit pUSE_SRL_FIFO = 0 ;
Expand Down Expand Up @@ -48,8 +46,6 @@
.pLLR_W ( pLLR_W ) ,
.pNODE_W ( pNODE_W ) ,
//
.pNORM_FACTOR ( pNORM_FACTOR ) ,
//
.pUSE_SC_MODE ( pUSE_SC_MODE ) ,
.pDO_LLR_INVERSION ( pDO_LLR_INVERSION ) ,
.pUSE_SRL_FIFO ( pUSE_SRL_FIFO )
Expand Down Expand Up @@ -142,7 +138,6 @@ module ldpc_dvb_dec_vnode
obusy
);

parameter int pNORM_FACTOR = 0;
parameter bit pDO_LLR_INVERSION = 0;
parameter bit pUSE_SRL_FIFO = 1; // use SRL based internal FIFO

Expand Down Expand Up @@ -189,7 +184,7 @@ module ldpc_dvb_dec_vnode
localparam int cNODE_TAG_W = $bits(cycle_idx_t);

localparam int cCNODE_FIFO_DEPTH_W = cNODE_PER_COL_NUM_W ;
localparam int cCNODE_FIFO_DAT_W = pNODE_W * cZC_MAX + cNODE_TAG_W;
localparam int cCNODE_FIFO_DAT_W = pNODE_W * cZC_MAX + cNODE_TAG_W + (pUSE_SC_MODE ? cNODE_STATE_W*cZC_MAX : 0);

//------------------------------------------------------------------------------------------------------
//
Expand Down Expand Up @@ -233,6 +228,7 @@ module ldpc_dvb_dec_vnode
logic ctrl__orslt_read ;
//
// vnode restore
logic restore__istate_init ;
zdat_t restore__ival ;
cycle_idx_t restore__ivnode_addr [cZC_MAX];
znode_state_t restore__ivnode_state ;
Expand Down Expand Up @@ -359,6 +355,12 @@ module ldpc_dvb_dec_vnode
for (int i = 0; i < cZC_MAX; i++) begin
cnode_fifo__iwdat[i*pNODE_W +: pNODE_W] = icnode[i];
end
//
if (pUSE_SC_MODE) begin
for (int i = 0; i < cZC_MAX; i++) begin
cnode_fifo__iwdat[cZC_MAX*pNODE_W + i*cNODE_STATE_W +: cNODE_STATE_W] = ivnode_state[i];
end
end
end

//
Expand Down Expand Up @@ -418,7 +420,6 @@ module ldpc_dvb_dec_vnode
#(
.pLLR_W ( pLLR_W ) ,
.pNODE_W ( pNODE_W ) ,
.pNORM_FACTOR ( pNORM_FACTOR ) ,
.pUSE_SC_MODE ( pUSE_SC_MODE )
)
restore
Expand All @@ -427,6 +428,8 @@ module ldpc_dvb_dec_vnode
.ireset ( ireset ) ,
.iclkena ( iclkena ) ,
//
.istate_init ( restore__istate_init ) ,
//
.ival ( restore__ival [g] ) ,
.ivnode_addr ( restore__ivnode_addr [g] ) ,
.ivnode_state ( restore__ivnode_state [g] ) ,
Expand Down Expand Up @@ -461,9 +464,15 @@ module ldpc_dvb_dec_vnode
//
// srl fifo has 1 tick delay
assign restore__ivnode_addr [g] = cnode_fifo__ordat[cCNODE_FIFO_DAT_W-1 -: cNODE_TAG_W];
assign restore__ivnode_state [g] = '0;
assign restore__icnode [g] = cnode_fifo__ordat[g*pNODE_W +: pNODE_W];

if (pUSE_SC_MODE) begin
assign restore__ivnode_state [g] = cnode_fifo__ordat[cZC_MAX*pNODE_W + g*cNODE_STATE_W +: cNODE_STATE_W];
end
else begin
assign restore__ivnode_state [g] = '0;
end

end
else begin

Expand All @@ -477,16 +486,32 @@ module ldpc_dvb_dec_vnode
end
//
// add + 1 tick delay to FIFO
restore__ivnode_addr [g] <= cnode_fifo__ordat[cCNODE_FIFO_DAT_W-1 -: cNODE_TAG_W];
restore__icnode [g] <= cnode_fifo__ordat[g*pNODE_W +: pNODE_W];
restore__ivnode_addr [g] <= cnode_fifo__ordat[cCNODE_FIFO_DAT_W-1 -: cNODE_TAG_W];
restore__icnode [g] <= cnode_fifo__ordat[g*pNODE_W +: pNODE_W];
if (pUSE_SC_MODE) begin
restore__ivnode_state [g] <= cnode_fifo__ordat[cZC_MAX*pNODE_W + g*cNODE_STATE_W +: cNODE_STATE_W];
end
else begin
restore__ivnode_state [g] <= '0;
end
end
end

assign restore__ivnode_state [g] = '0;
end
end
endgenerate

//------------------------------------------------------------------------------------------------------
// init sc state at first iteration. Hold it in register
//------------------------------------------------------------------------------------------------------

always_ff @(posedge iclk) begin
if (iclkena) begin
if (istart) begin
restore__istate_init <= iload_iter;
end
end
end

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
Expand All @@ -499,21 +524,15 @@ module ldpc_dvb_dec_vnode

//------------------------------------------------------------------------------------------------------
// obusy is look ahead signal for control
// there is 4 tick betwen write/read to node ram
// this logic save 2 tick for each iteration
// there is 4 tick betwen write/read to node ram this logic + matrix reorder save it for each iteration
//------------------------------------------------------------------------------------------------------

always_ff @(posedge iclk or posedge ireset) begin
if (ireset) begin
obusy <= 1'b0;
end
else if (iclkena) begin
if (pUSE_SRL_FIFO) begin
obusy <= ctrl__oread | !cnode_fifo__oempty;
end
else begin
obusy <= cnode_fifo__orval | !cnode_fifo__oempty; // fifo_empty use because there can be holes in oval flow (!!!)
end
obusy <= !cnode_fifo__oempty; // fifo_empty use because there can be holes in oval flow (!!!)
end
end

Expand Down
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