Space Invaders implementation on iCEBreaker FPGA development board

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade

BaseJump STL: A Standard Template Library for SystemVerilog

LaTeX class file for writing dissertations at UC San Diego

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Yosys Open SYnthesis Suite