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Arm64: SVE/SVE2 encodings #94285

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Merged
merged 7 commits into from
Nov 8, 2023
Merged

Arm64: SVE/SVE2 encodings #94285

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4ddc65e
Add encodings for SVE
kunalspathak Nov 1, 2023
7fa39fb
Adjust the offsets
kunalspathak Nov 2, 2023
2d4aeb8
jit format
kunalspathak Nov 2, 2023
f28a546
fix the build for riscV64
kunalspathak Nov 2, 2023
1518bf9
Address review feedback from Bruce
kunalspathak Nov 7, 2023
7948f4d
Rename files to remove _
kunalspathak Nov 7, 2023
75d89ea
forgot to rename file names in other places
kunalspathak Nov 7, 2023
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2 changes: 2 additions & 0 deletions src/coreclr/jit/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -398,8 +398,10 @@ set( JIT_I386_HEADERS ${JIT_AMD64_HEADERS} )
set( JIT_ARM64_HEADERS
emitarm64.h
emitfmtsarm64.h
emitfmtsarm64sve.h
hwintrinsiclistarm64.h
instrsarm64.h
instrsarm64sve.h
registerarm64.h
simdashwintrinsiclistarm64.h
)
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8 changes: 8 additions & 0 deletions src/coreclr/jit/emit.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,10 @@ const char* emitter::emitIfName(unsigned f)
static const char* const ifNames[] = {
#define IF_DEF(en, op1, op2) "IF_" #en,
#include "emitfmts.h"
#if defined(TARGET_ARM64)
#define IF_DEF(en, op1, op2) "IF_" #en,
#include "emitfmtsarm64sve.h"
#endif
};

static char errBuff[32];
Expand Down Expand Up @@ -3767,6 +3771,10 @@ emitter::instrDesc* emitter::emitNewInstrCallDir(int argCnt,
const BYTE emitter::emitFmtToOps[] = {
#define IF_DEF(en, op1, op2) ID_OP_##op2,
#include "emitfmts.h"
#if defined(TARGET_ARM64)
#define IF_DEF(en, op1, op2) ID_OP_##op2,
#include "emitfmtsarm64sve.h"
#endif
};

#ifdef DEBUG
Expand Down
36 changes: 22 additions & 14 deletions src/coreclr/jit/emit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -565,7 +565,10 @@ class emitter
{
#define IF_DEF(en, op1, op2) IF_##en,
#include "emitfmts.h"

#if defined(TARGET_ARM64)
#define IF_DEF(en, op1, op2) IF_##en,
#include "emitfmtsarm64sve.h"
#endif
IF_COUNT
};

Expand Down Expand Up @@ -628,8 +631,8 @@ class emitter
#define MAX_ENCODED_SIZE 15
#elif defined(TARGET_ARM64)
#define INSTR_ENCODED_SIZE 4
static_assert_no_msg(INS_count <= 1024);
instruction _idIns : 10;
static_assert_no_msg(INS_count <= 2048);
instruction _idIns : 11;
#elif defined(TARGET_LOONGARCH64)
// TODO-LoongArch64: not include SIMD-vector.
static_assert_no_msg(INS_count <= 512);
Expand All @@ -647,6 +650,9 @@ class emitter
unsigned _idCodeSize : 5; // the instruction(s) size of this instrDesc described.
#elif defined(TARGET_RISCV64)
unsigned _idCodeSize : 6; // the instruction(s) size of this instrDesc described.
#elif defined(TARGET_ARM64)
static_assert_no_msg(IF_COUNT <= 1024);
insFormat _idInsFmt : 10;
#else
static_assert_no_msg(IF_COUNT <= 256);
insFormat _idInsFmt : 8;
Expand Down Expand Up @@ -712,7 +718,7 @@ class emitter
// x86: 17 bits
// amd64: 17 bits
// arm: 16 bits
// arm64: 18 bits
// arm64: 21 bits
// loongarch64: 14 bits
// risc-v: 14 bits

Expand All @@ -722,10 +728,13 @@ class emitter
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16, 5=32
// At this point we have fully consumed first DWORD so that next field
// doesn't cross a byte boundary.
#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
#elif defined(TARGET_ARM64)
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16
insOpts _idInsOpt : 6; // options for instructions
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
/* _idOpSize defined below. */
#else
opSize _idOpSize : 2; // operand size: 0=1 , 1=2 , 2=4 , 3=8
opSize _idOpSize : 2; // operand size: 0=1 , 1=2 , 2=4 , 3=8
#endif // TARGET_ARM64 || TARGET_LOONGARCH64 || TARGET_RISCV64

// On Amd64, this is where the second DWORD begins
Expand Down Expand Up @@ -754,7 +763,7 @@ class emitter
// x86: 38 bits
// amd64: 38 bits
// arm: 32 bits
// arm64: 32 bits
// arm64: 44 bits
// loongarch64: 28 bits
// risc-v: 28 bits

Expand All @@ -774,8 +783,7 @@ class emitter
#endif // TARGET_XARCH

#ifdef TARGET_ARM64
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16
insOpts _idInsOpt : 6; // options for instructions

unsigned _idLclVar : 1; // access a local on stack
unsigned _idLclVarPair : 1 // carries information for 2 GC lcl vars.
#endif
Expand Down Expand Up @@ -808,7 +816,7 @@ class emitter
// x86: 47 bits
// amd64: 47 bits
// arm: 48 bits
// arm64: 50 bits
// arm64: 53 bits
// loongarch64: 46 bits
// risc-v: 46 bits

Expand All @@ -821,7 +829,7 @@ class emitter
#if defined(TARGET_ARM)
#define ID_EXTRA_BITFIELD_BITS (16)
#elif defined(TARGET_ARM64)
#define ID_EXTRA_BITFIELD_BITS (18)
#define ID_EXTRA_BITFIELD_BITS (21)
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
#define ID_EXTRA_BITFIELD_BITS (14)
#elif defined(TARGET_XARCH)
Expand Down Expand Up @@ -863,7 +871,7 @@ class emitter
// x86: 53/49 bits
// amd64: 54/49 bits
// arm: 54/50 bits
// arm64: 57/52 bits
// arm64: 60/55 bits
// loongarch64: 53/48 bits
// risc-v: 53/48 bits
CLANG_FORMAT_COMMENT_ANCHOR;
Expand All @@ -880,7 +888,7 @@ class emitter
// x86: 11/15 bits
// amd64: 10/15 bits
// arm: 10/14 bits
// arm64: 7/12 bits
// arm64: 4/9 bits
// loongarch64: 11/16 bits
// risc-v: 11/16 bits
CLANG_FORMAT_COMMENT_ANCHOR;
Expand Down Expand Up @@ -1132,7 +1140,7 @@ class emitter
_idCodeSize = sz;
}
#elif defined(TARGET_RISCV64)
unsigned idCodeSize() const
unsigned idCodeSize() const
{
return _idCodeSize;
}
Expand Down
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