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Handle MultiRegNode in gtGetRegMask() #93576

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Merged
merged 12 commits into from
Oct 20, 2023
Merged

Handle MultiRegNode in gtGetRegMask() #93576

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297bfd7
Handle MultiRegNode in gtGetRegMask()
kunalspathak Oct 16, 2023
76b12a0
fix build error
kunalspathak Oct 16, 2023
c18ed2b
Use IsCopyOrReloadOfMultiRegNode()
kunalspathak Oct 18, 2023
54e1336
Handle gtHasReg()
kunalspathak Oct 18, 2023
b0b12f5
Handle gtProduceReg()
kunalspathak Oct 18, 2023
bb57098
Refactor the code for gtHasReg()
kunalspathak Oct 19, 2023
9c82ebc
Refactor the code for genProduceReg()
kunalspathak Oct 19, 2023
0488e56
some more refactoring
kunalspathak Oct 19, 2023
4969b4f
Only enable for arm64
kunalspathak Oct 19, 2023
1ca2d8f
remove the temp test for arm64
kunalspathak Oct 19, 2023
d189993
Revert the handling in genProduceReg() and gtHasReg()
kunalspathak Oct 20, 2023
f600d90
Revert the handling in genProduceReg() and gtHasReg()
kunalspathak Oct 20, 2023
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14 changes: 9 additions & 5 deletions src/coreclr/jit/codegenlinear.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1453,7 +1453,11 @@ regNumber CodeGen::genConsumeReg(GenTree* tree, unsigned multiRegIndex)
}
else
{
gcInfo.gcMarkRegSetNpt(tree->gtGetRegMask());
regNumber regAtIndex = tree->GetRegByIndex(multiRegIndex);
if (regAtIndex != REG_NA)
{
gcInfo.gcMarkRegSetNpt(genRegMask(regAtIndex));
}
}
return reg;
}
Expand Down Expand Up @@ -2230,14 +2234,14 @@ void CodeGen::genProduceReg(GenTree* tree)
else if (tree->IsMultiRegLclVar())
{
assert(compiler->lvaEnregMultiRegVars);
GenTreeLclVar* lclNode = tree->AsLclVar();
LclVarDsc* varDsc = compiler->lvaGetDesc(lclNode);
unsigned regCount = varDsc->lvFieldCnt;
const GenTreeLclVar* lclNode = tree->AsLclVar();
LclVarDsc* varDsc = compiler->lvaGetDesc(lclNode);
unsigned regCount = varDsc->lvFieldCnt;
for (unsigned i = 0; i < regCount; i++)
{
if (!lclNode->IsLastUse(i))
{
regNumber reg = lclNode->GetRegByIndex(i);
regNumber reg = lclNode->GetRegNumByIdx(i);
if (reg != REG_NA)
{
var_types type = compiler->lvaGetDesc(varDsc->lvFieldLclStart + i)->TypeGet();
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -836,7 +836,7 @@ bool GenTree::gtHasReg(Compiler* comp) const
{
assert(comp != nullptr);
const GenTreeLclVar* lclNode = AsLclVar();
const unsigned regCount = GetMultiRegCount(comp);
const unsigned regCount = lclNode->GetFieldCount(comp);
// A Multi-reg local vars is said to have regs,
// if it has valid regs in any of the positions.
for (unsigned i = 0; i < regCount; i++)
Expand Down
5 changes: 4 additions & 1 deletion src/coreclr/jit/lsraarm64.cpp
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Expand Up @@ -1624,7 +1624,10 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, int* pDstCou
assert(intrin.op2 != nullptr);
assert(intrin.op3 != nullptr);
assert(isRMW);
srcCount += BuildOperandUses(intrin.op2);
if (!intrin.op2->isContainedIntOrIImmed())
{
srcCount += BuildOperandUses(intrin.op2);
}

assert(intrinsicTree->OperIsMemoryLoadOrStore());
srcCount += BuildAddrUses(intrin.op3);
Expand Down