JIT: Propagate multi-reg-index for upper-vector-restore ref positions #88380
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
`LinearScan::resolveRegisters` will write the register back to the IR
node for an upper-vector-restore RP, so without this propagation we
would overwrite the register assignment for an unrelated field.
For example, for IR like
```scala
N001 ( 9, 6) [000090] m------N--- t90 = LCL_VAR struct<JIT.HardwareIntrinsics.Arm._AdvSimd.SimpleTernaryOpTest__AbsoluteDifferenceWideningUpperAndAdd_Vector128_UInt32+TestStruct, 48>(P) V00 loc0
▌ simd16 field V00._fld1 (fldOffset=0x0) -> V14 tmp10 (last use)
▌ simd16 field V00._fld2 (fldOffset=0x10) -> V15 tmp11 (last use)
▌ simd16 field V00._fld3 (fldOffset=0x20) -> V16 tmp12 (last use) $540
┌──▌ t90 struct
N002 ( 10, 7) [000091] ----------- ▌ RETURN struct $VN.Void
```
we could build ref positions such as
```
[000091] 449.dotnet#639 U14 UVRs UVRes NA │ │ │ │ │ │ │ │ │ │ │ │ │V16a│ │ │ │
449.dotnet#640 d0 Fixd Keep d0 │ │ │ │ │ │ │ │ │ │ │ │ │V16a│ │ │ │
449.dotnet#641 V14 Use * ReLod d0 │ │ │ │ │ │ │ │ │ │ │V14a│ │V16a│ │ │ │
Keep d0 │ │ │ │ │ │ │ │ │ │ │V14i│ │V16a│ │ │ │
449.dotnet#642 U15 UVRs UVRes NA │ │ │ │ │ │ │ │ │ │ │ │ │V16a│ │ │ │
449.dotnet#643 d1 Fixd Keep d1 │ │ │ │ │ │ │ │ │ │ │ │ │V16a│ │ │ │
449.dotnet#644 V15 Use * ReLod d1 │ │ │ │ │ │ │ │ │ │ │ │V15a│V16a│ │ │ │
Keep d1 │ │ │ │ │ │ │ │ │ │ │ │V15i│V16a│ │ │ │
449.dotnet#645 d2 Fixd Keep d2 │ │ │ │ │ │ │ │ │ │ │ │ │V16a│ │ │ │
449.dotnet#646 V16 Use * Keep d2 │ │ │ │ │ │ │ │ │ │ │ │ │V16i│ │ │ │
```
When writing back register assignments the upper-vector-restore at dotnet#642
ended up overwriting the assignment for the first field on [000090],
resulting in
```scala
N447 ( 9, 6) [000090] m------N--z t90 = LCL_VAR struct<JIT.HardwareIntrinsics.Arm._AdvSimd.SimpleTernaryOpTest__AbsoluteDifferenceWideningUpperAndAdd_Vector128_UInt32+TestStruct, 48>(P) V00 loc0 NA
▌ simd16 field V00._fld1 (fldOffset=0x0) -> V14 tmp10 (last use)
▌ simd16 field V00._fld2 (fldOffset=0x10) -> V15 tmp11 (last use)
▌ simd16 field V00._fld3 (fldOffset=0x20) -> V16 tmp12 d2 (last use) REG NA,d1,d2 $540
┌──▌ t90 struct
N449 ( 10, 7) [000091] ----------- ▌ RETURN struct REG NA $VN.Void
```
(note the REG NA instead of REG d0).
ghost
added
the
area-CodeGen-coreclr
|
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue Details
For example, for IR like N001 ( 9, 6) [000090] m------N--- t90 = LCL_VAR struct<JIT.HardwareIntrinsics.Arm._AdvSimd.SimpleTernaryOpTest__AbsoluteDifferenceWideningUpperAndAdd_Vector128_UInt32+TestStruct, 48>(P) V00 loc0
▌ simd16 field V00._fld1 (fldOffset=0x0) -> V14 tmp10 (last use)
▌ simd16 field V00._fld2 (fldOffset=0x10) -> V15 tmp11 (last use)
▌ simd16 field V00._fld3 (fldOffset=0x20) -> V16 tmp12 (last use) $540
┌──▌ t90 struct
N002 ( 10, 7) [000091] ----------- ▌ RETURN struct $VN.Voidwe could build ref positions such as When writing back register assignments the upper-vector-restore at N447 ( 9, 6) [000090] m------N--z t90 = LCL_VAR struct<JIT.HardwareIntrinsics.Arm._AdvSimd.SimpleTernaryOpTest__AbsoluteDifferenceWideningUpperAndAdd_Vector128_UInt32+TestStruct, 48>(P) V00 loc0 NA
▌ simd16 field V00._fld1 (fldOffset=0x0) -> V14 tmp10 (last use)
▌ simd16 field V00._fld2 (fldOffset=0x10) -> V15 tmp11 (last use)
▌ simd16 field V00._fld3 (fldOffset=0x20) -> V16 tmp12 d2 (last use) REG NA,d1,d2 $540
┌──▌ t90 struct
N449 ( 10, 7) [000091] ----------- ▌ RETURN struct REG NA $VN.Void(note the REG NA instead of REG d0).
|
|
/azp run runtime-coreclr jitstress, runtime-coreclr libraries-jitstress, runtime-coreclr jitstressregs |
|
Azure Pipelines successfully started running 3 pipeline(s). |
This was referenced Jul 4, 2023
|
/azp run runtime-coreclr superpmi-diffs |
|
Azure Pipelines successfully started running 1 pipeline(s). |
|
cc @dotnet/jit-contrib PTAL @kunalspathak No diffs. Fixes a problem I hit in #84122 with JitStressRegs=2. |
|
I am assuming the jitstress failures are unrelated? |
Yep, they are known according to build analysis. |
Sign up for free
to subscribe to this conversation on GitHub.
Already have an account?
Sign in.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
LinearScan::resolveRegisterswill write the register back to the IR node for an upper-vector-restore RP, so without this propagation we would overwrite the register assignment for an unrelated field.For example, for IR like
we could build ref positions such as
When writing back register assignments the upper-vector-restore at
449.#642ended up overwriting the assignment for the first field on [000090], resulting in(note the REG NA instead of REG d0).