Improving the SIMD codegen for SIMD12 load/store

[tannergooding]

This adds support for containment on TYP_SIMD12 loads/stores and improves the codegen to require less temporary registers and use better instructions when available.

Improved Load:

- lea      rax, bword ptr [rcx+30H]
- vmovss   xmm0, dword ptr [rax+08H]
- vmovsd   xmm1, qword ptr [rax]
- vshufps  xmm1, xmm0, 68
+ vmovsd   xmm0, qword ptr [rcx+30H]
+ vinsertps xmm0, dword ptr [rcx+38H], 2

Improved Store:

- vmovsd   qword ptr [rdx], xmm1
- vpshufd  xmm0, xmm1, 2
- vmovss   dword ptr [rdx+08H], xmm0
+ vmovsd   qword ptr [rdx], xmm0
+ vextractps dword ptr [rdx+08H], xmm0, 2

Combined this saves 9 bytes of codegen and improves the PerScore by 1.5

Total diffs are all relatively similar. Emitting vmovsd + vinsertps or vmovsd + vextractps and removing now unnecessary lea in favor of containing them.

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Issue Details

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This adds support for containment on TYP_SIMD12 loads/stores and improves the codegen to require less temporary registers and use better instructions when available.

Improved Load:

- lea      rax, bword ptr [rcx+30H]
- vmovss   xmm0, dword ptr [rax+08H]
- vmovsd   xmm1, qword ptr [rax]
- vshufps  xmm1, xmm0, 68
+ vmovsd   xmm0, qword ptr [rcx+30H]
+ vinsertps xmm0, dword ptr [rcx+38H], 2

Improved Store:

- vmovsd   qword ptr [rdx], xmm1
- vpshufd  xmm0, xmm1, 2
- vmovss   dword ptr [rdx+08H], xmm0
+ vmovsd   qword ptr [rdx], xmm0
+ vextractps dword ptr [rdx+08H], xmm0, 2

Combined this saves 9 bytes of codegen and improves the PerScore by 1.5

Total diffs are all relatively similar. Emitting vmovsd + vinsertps or vmovsd + vextractps and removing now unnecessary lea in favor of containing them.

Author:	tannergooding
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	-

[tannergooding]

CC. @dotnet/jit-contrib, this should be ready for review.

Gives some small size savings for x64 (~2k bytes in fullopts and ~0.5k bytes in minopts) and a small TP win on x64

[tannergooding]

/azp run runtime-coreclr jitstress-isas-x86, runtime-coreclr jitstress-isas-arm, runtime-coreclr outerloop

[azure-pipelines]

Azure Pipelines successfully started running 3 pipeline(s).

[tannergooding]

/azp run runtime-coreclr jitstress-isas-x86, runtime-coreclr jitstress-isas-arm, runtime-coreclr outerloop

[azure-pipelines]

Azure Pipelines successfully started running 3 pipeline(s).

[tannergooding]

Fixed the jitstress failure. Results in ~3.3k savings on x86/x64 and a -0.01% TP improvement

[TIHan]

This looks good to me. There seems to be a failure for ARM though, but it looks like just one test case at the moment.

[tannergooding]

There seems to be a failure for ARM though, but it looks like just one test case at the moment.

It's an unrelated/existing GC timeout. I've retriggered it and it should pass on rerun.

[tannergooding]

/azp run runtime-coreclr jitstress-isas-x86, runtime-coreclr jitstress-isas-arm, runtime-coreclr outerloop

[azure-pipelines]

Azure Pipelines successfully started running 3 pipeline(s).