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Fixing assert on variable live range for simd12 LCL / STORE_LCL #79182

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Merged
merged 8 commits into from
Dec 9, 2022
Merged

Fixing assert on variable live range for simd12 LCL / STORE_LCL #79182

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c9fe145
Adding jitdump for varible debug info
BrianBohe Dec 3, 2022
1dd4e66
Forcing home and live update after SIMD12 store lcl
BrianBohe Dec 3, 2022
033ea8f
Formatting file
Dec 3, 2022
a706cba
Add missing case of targetReg in genStoreLclTypeSIMD12()
kunalspathak Dec 8, 2022
f8f07c5
Fix liveness update for genStoreLclFld() and genStoreLclVar on x64
kunalspathak Dec 8, 2022
9573df0
Fix liveness update for genStoreLclTypeSIMD12() on arm64
kunalspathak Dec 8, 2022
d399b8c
Fix and unifying genStoreLclFld/LclVar on x64
Dec 8, 2022
154ac7a
Revert "Ignoring test regression runtime_63354 in x86 (#79358)"
BrianBohe Dec 8, 2022
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13 changes: 11 additions & 2 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5577,8 +5577,9 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)

GenTreeLclVarCommon* lclVar = treeNode->AsLclVarCommon();

unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);
assert(varNum < compiler->lvaCount);

GenTree* op1 = lclVar->gtGetOp1();
Expand All @@ -5594,6 +5595,10 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
// Store upper 4 bytes
GetEmitter()->emitIns_S_R(ins_Store(TYP_FLOAT), EA_4BYTE, REG_ZR, varNum, offs + 8);

// Update life after instruction emitted
genUpdateLife(treeNode);
varDsc->SetRegNum(REG_STK);

return;
}

Expand All @@ -5613,6 +5618,10 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
// Need an additional integer register to extract upper 4 bytes from data.
regNumber tmpReg = lclVar->GetSingleTempReg();
GetEmitter()->emitStoreSIMD12ToLclOffset(varNum, offs, operandReg, tmpReg);

// Update life after instruction emitted
genUpdateLife(treeNode);
varDsc->SetRegNum(REG_STK);
}
}

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1 change: 1 addition & 0 deletions src/coreclr/jit/codegencommon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8769,6 +8769,7 @@ void CodeGenInterface::VariableLiveKeeper::VariableLiveDescriptor::endLiveRangeA
// Using [close, open) ranges so as to not compute the size of the last instruction
m_VariableLiveRanges->back().m_EndEmitLocation.CaptureLocation(emit);

JITDUMP("Closing debug range.\n");
// No m_EndEmitLocation has to be Valid
noway_assert(m_VariableLiveRanges->back().m_EndEmitLocation.Valid());
}
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31 changes: 20 additions & 11 deletions src/coreclr/jit/codegenxarch.cpp
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Expand Up @@ -4848,8 +4848,6 @@ void CodeGen::genCodeForStoreLclFld(GenTreeLclFld* tree)
assert(tree->OperIs(GT_STORE_LCL_FLD));

var_types targetType = tree->TypeGet();
GenTree* op1 = tree->gtGetOp1();

noway_assert(targetType != TYP_STRUCT);

#ifdef FEATURE_SIMD
Expand All @@ -4861,26 +4859,26 @@ void CodeGen::genCodeForStoreLclFld(GenTreeLclFld* tree)
}
#endif // FEATURE_SIMD

GenTree* op1 = tree->gtGetOp1();
regNumber targetReg = tree->GetRegNum();
unsigned lclNum = tree->GetLclNum();
LclVarDsc* varDsc = compiler->lvaGetDesc(lclNum);

assert(varTypeUsesFloatReg(targetType) == varTypeUsesFloatReg(op1));
assert(genTypeSize(genActualType(targetType)) == genTypeSize(genActualType(op1->TypeGet())));

genConsumeRegs(op1);

if (op1->OperIs(GT_BITCAST) && op1->isContained())
{
regNumber targetReg = tree->GetRegNum();
GenTree* bitCastSrc = op1->gtGetOp1();
var_types srcType = bitCastSrc->TypeGet();
noway_assert(!bitCastSrc->isContained());

if (targetReg == REG_NA)
{
unsigned lclNum = tree->GetLclNum();
LclVarDsc* varDsc = compiler->lvaGetDesc(lclNum);

GetEmitter()->emitIns_S_R(ins_Store(srcType, compiler->isSIMDTypeLocalAligned(lclNum)),
emitTypeSize(targetType), bitCastSrc->GetRegNum(), lclNum, tree->GetLclOffs());
varDsc->SetRegNum(REG_STK);
}
else
{
Expand All @@ -4893,7 +4891,15 @@ void CodeGen::genCodeForStoreLclFld(GenTreeLclFld* tree)
}

// Updating variable liveness after instruction was emitted
genUpdateLife(tree);
if (targetReg != REG_NA)
{
genProduceReg(tree);
}
else
{
genUpdateLife(tree);
varDsc->SetRegNum(REG_STK);
}
}

//------------------------------------------------------------------------
Expand Down Expand Up @@ -4965,8 +4971,6 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
{
emit->emitIns_S_R(ins_Store(srcType, compiler->isSIMDTypeLocalAligned(lclNum)),
emitTypeSize(targetType), bitCastSrc->GetRegNum(), lclNum, 0);
genUpdateLife(lclNode);
varDsc->SetRegNum(REG_STK);
}
else
{
Expand All @@ -4978,7 +4982,6 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
// stack store
emit->emitInsStoreLcl(ins_Store(targetType, compiler->isSIMDTypeLocalAligned(lclNum)),
emitTypeSize(targetType), lclNode);
varDsc->SetRegNum(REG_STK);
}
else
{
Expand Down Expand Up @@ -5015,10 +5018,16 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
emitTypeSize(targetType));
}
}
// Updating variable liveness after instruction was emitted
if (targetReg != REG_NA)
{
genProduceReg(lclNode);
}
else
{
genUpdateLife(lclNode);
varDsc->SetRegNum(REG_STK);
}
}
}

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3 changes: 0 additions & 3 deletions src/coreclr/jit/emitxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4500,9 +4500,6 @@ void emitter::emitInsStoreLcl(instruction ins, emitAttr attr, GenTreeLclVarCommo
assert(!data->isContained());
emitIns_S_R(ins, attr, data->GetRegNum(), varNode->GetLclNum(), 0);
}

// Updating variable liveness after instruction was emitted
codeGen->genUpdateLife(varNode);
}

//------------------------------------------------------------------------
Expand Down
43 changes: 30 additions & 13 deletions src/coreclr/jit/simdcodegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -939,31 +939,48 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
assert((treeNode->OperGet() == GT_STORE_LCL_FLD) || (treeNode->OperGet() == GT_STORE_LCL_VAR));

const GenTreeLclVarCommon* lclVar = treeNode->AsLclVarCommon();

unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
assert(varNum < compiler->lvaCount);

GenTree* op1 = lclVar->gtOp1;

assert(!op1->isContained());
regNumber targetReg = treeNode->GetRegNum();
regNumber operandReg = genConsumeReg(op1);

// store lower 8 bytes
GetEmitter()->emitIns_S_R(ins_Store(TYP_DOUBLE), EA_8BYTE, operandReg, varNum, offs);

if (!op1->IsVectorZero())
if (targetReg != REG_NA)
{
regNumber tmpReg = treeNode->GetSingleTempReg();
assert(!GetEmitter()->isGeneralRegister(targetReg));

// Extract upper 4-bytes from operandReg
GetEmitter()->emitIns_R_R_I(INS_pshufd, emitActualTypeSize(TYP_SIMD16), tmpReg, operandReg, 0x02);
inst_Mov(treeNode->TypeGet(), targetReg, operandReg, /* canSkip */ true);

operandReg = tmpReg;
genProduceReg(treeNode);
}
else
{
// store lower 8 bytes
GetEmitter()->emitIns_S_R(ins_Store(TYP_DOUBLE), EA_8BYTE, operandReg, varNum, offs);

if (!op1->IsVectorZero())
{
regNumber tmpReg = treeNode->GetSingleTempReg();

// Store upper 4 bytes
GetEmitter()->emitIns_S_R(ins_Store(TYP_FLOAT), EA_4BYTE, operandReg, varNum, offs + 8);
// Extract upper 4-bytes from operandReg
GetEmitter()->emitIns_R_R_I(INS_pshufd, emitActualTypeSize(TYP_SIMD16), tmpReg, operandReg, 0x02);

operandReg = tmpReg;
}

// Store upper 4 bytes
GetEmitter()->emitIns_S_R(ins_Store(TYP_FLOAT), EA_4BYTE, operandReg, varNum, offs + 8);

// Update the life of treeNode
genUpdateLife(treeNode);

LclVarDsc* varDsc = compiler->lvaGetDesc(varNum);
varDsc->SetRegNum(REG_STK);
}
}

//-----------------------------------------------------------------------------
Expand Down
3 changes: 0 additions & 3 deletions src/tests/issues.targets
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Original file line number Diff line number Diff line change
Expand Up @@ -280,9 +280,6 @@
<ExcludeList Include="$(XunitTestBinBase)/JIT/Regression/JitBlue/Runtime_31615/Runtime_31615/*">
<Issue>https://github.com/dotnet/runtime/issues/79170</Issue>
</ExcludeList>
<ExcludeList Include="$(XunitTestBinBase)/JIT/Regression/JitBlue/Runtime_63354/Runtime_63354/**">
<Issue>https://github.com/dotnet/runtime/issues/78898</Issue>
</ExcludeList>
</ItemGroup>

<!-- Windows arm32 specific excludes -->
Expand Down