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Ensure the JIT view of InstructionSets is correct in the face of JitConfig switches #62420

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Merged
merged 9 commits into from
Jan 12, 2022
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Ensure the JIT view of InstructionSets is correct in the face of JitConfig switches #62420

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283ce7c
Adding a regression test for dotnet/runtime#60035
tannergooding Dec 6, 2021
d4a0438
Add the correct "ISA implications" for Vector64/128
tannergooding Dec 5, 2021
cae62e8
Moving the `COMPlus_Enable*` HWIntrinsic ISA switches to the VM
tannergooding Dec 6, 2021
93d993a
Ensure Set64BitInstructionSetVariants is called before EnsureValidIns…
tannergooding Jan 4, 2022
816cd1e
Ensure opts.compSupportsISA isn't overwritten to 0
tannergooding Jan 4, 2022
c36f9a3
Ensure that Lzcnt is dependent on X86Base and AvxVnni is dependent on…
tannergooding Jan 4, 2022
356d8bd
Adding x64, x86, and Arm64 specific views to help with debugging CorI…
tannergooding Jan 6, 2022
869f824
Keep the JIT in charge of "artificial" ISAs
tannergooding Jan 6, 2022
41bf5cd
Update JitBlue/Runtime_34587 to also validate the xplat SIMD types
tannergooding Jan 6, 2022
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41 changes: 35 additions & 6 deletions src/coreclr/inc/clrconfigvalues.h
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Expand Up @@ -348,14 +348,8 @@ RETAIL_CONFIG_DWORD_INFO(INTERNAL_JitVNMapSelBudget, W("JitVNMapSelBudget"), 100
#else // !(defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM64))
#define EXTERNAL_FeatureSIMD_Default 0
#endif // !(defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM64))
#if defined(TARGET_AMD64) || defined(TARGET_X86)
#define EXTERNAL_JitEnableAVX_Default 1
#else // !(defined(TARGET_AMD64) || defined(TARGET_X86)
#define EXTERNAL_JitEnableAVX_Default 0
#endif // !(defined(TARGET_AMD64) || defined(TARGET_X86)
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_FeatureSIMD, W("FeatureSIMD"), EXTERNAL_FeatureSIMD_Default, "Enable SIMD intrinsics recognition in System.Numerics.dll and/or System.Numerics.Vectors.dll")
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@tannergooding tannergooding Dec 6, 2021 •
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We need to do something about FeatureSIMD. Originally it was intended to be a workaround in case the System.Numerics.Vector* logic had issues (back before hardware intrinsics were even a concept).

However, given how critical SIMD is to the ABI and even basic operations in the JIT for x64 and Arm64; I think it might be better to actually remove the public facing flag here and leave it only a compile level switch for x86 Unix and Arm32 (the two targets where FEATURE_SIMD == 0 today).

If we don't remove it, then we need to also have the VM take it into account for certain ISAs (basically everything except X86Base, Lzcnt, and ArmBase; Bmi1 and Bmi2 are "scalar" but not included because they depend on EnableAvx=1 due to the VEX encoding).

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-- If we are fine with removing flags, EXTERNAL_EnableSSE3_4 is also legacy and unnecessary as it has the same meaning as EnableSSE3

RETAIL_CONFIG_DWORD_INFO(INTERNAL_SIMD16ByteOnly, W("SIMD16ByteOnly"), 0, "Limit maximum SIMD vector length to 16 bytes (used by x64_arm64_altjit)")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX, W("EnableAVX"), EXTERNAL_JitEnableAVX_Default, "Enable AVX instruction set for wide operations as default")
RETAIL_CONFIG_DWORD_INFO(UNSUPPORTED_TrackDynamicMethodDebugInfo, W("TrackDynamicMethodDebugInfo"), 0, "Specifies whether debug info should be generated and tracked for dynamic methods")

#ifdef FEATURE_MULTICOREJIT
Expand Down Expand Up @@ -724,6 +718,41 @@ RETAIL_CONFIG_DWORD_INFO(INTERNAL_GDBJitEmitDebugFrame, W("GDBJitEmitDebugFrame"
#endif
#endif

//
// Hardware Intrinsic ISAs
//
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic, W("EnableHWIntrinsic"), 1, "Allows Base+ hardware intrinsics to be disabled")

#if defined(TARGET_AMD64) || defined(TARGET_X86)
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAES, W("EnableAES"), 1, "Allows AES+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX, W("EnableAVX"), 1, "Allows AVX+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX2, W("EnableAVX2"), 1, "Allows AVX2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI, W("EnableAVXVNNI"), 1, "Allows AVX VNNI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1, W("EnableBMI1"), 1, "Allows BMI1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2, W("EnableBMI2"), 1, "Allows BMI2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableFMA, W("EnableFMA"), 1, "Allows FMA+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableLZCNT, W("EnableLZCNT"), 1, "Allows LZCNT+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnablePCLMULQDQ, W("EnablePCLMULQDQ"), 1, "Allows PCLMULQDQ+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnablePOPCNT, W("EnablePOPCNT"), 1, "Allows POPCNT+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE, W("EnableSSE"), 1, "Allows SSE+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE2, W("EnableSSE2"), 1, "Allows SSE2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE3, W("EnableSSE3"), 1, "Allows SSE3+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE3_4, W("EnableSSE3_4"), 1, "Allows SSE3+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE41, W("EnableSSE41"), 1, "Allows SSE4.1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE42, W("EnableSSE42"), 1, "Allows SSE4.2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSSE3, W("EnableSSSE3"), 1, "Allows SSSE3+ hardware intrinsics to be disabled")
#elif defined(TARGET_ARM64)
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64AdvSimd, W("EnableArm64AdvSimd"), 1, "Allows Arm64 AdvSimd+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Aes, W("EnableArm64Aes"), 1, "Allows Arm64 Aes+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Atomics, W("EnableArm64Atomics"), 1, "Allows Arm64 Atomics+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Crc32, W("EnableArm64Crc32"), 1, "Allows Arm64 Crc32+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Dczva, W("EnableArm64Dczva"), 1, "Allows Arm64 Dczva+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Dp, W("EnableArm64Dp"), 1, "Allows Arm64 Dp+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rdm, W("EnableArm64Rdm"), 1, "Allows Arm64 Rdm+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha1, W("EnableArm64Sha1"), 1, "Allows Arm64 Sha1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sha256"), 1, "Allows Arm64 Sha256+ hardware intrinsics to be disabled")
#endif

///
/// Uncategorized
///
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16 changes: 16 additions & 0 deletions src/coreclr/inc/corinfoinstructionset.h
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Expand Up @@ -282,6 +282,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_Sha1);
if (resultflags.HasInstructionSet(InstructionSet_Sha256) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
resultflags.RemoveInstructionSet(InstructionSet_Sha256);
if (resultflags.HasInstructionSet(InstructionSet_Vector64) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
resultflags.RemoveInstructionSet(InstructionSet_Vector64);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64))
Expand Down Expand Up @@ -376,12 +380,18 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_BMI2);
if (resultflags.HasInstructionSet(InstructionSet_FMA) && !resultflags.HasInstructionSet(InstructionSet_AVX))
resultflags.RemoveInstructionSet(InstructionSet_FMA);
if (resultflags.HasInstructionSet(InstructionSet_LZCNT) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
resultflags.RemoveInstructionSet(InstructionSet_LZCNT);
if (resultflags.HasInstructionSet(InstructionSet_PCLMULQDQ) && !resultflags.HasInstructionSet(InstructionSet_SSE2))
resultflags.RemoveInstructionSet(InstructionSet_PCLMULQDQ);
if (resultflags.HasInstructionSet(InstructionSet_POPCNT) && !resultflags.HasInstructionSet(InstructionSet_SSE42))
resultflags.RemoveInstructionSet(InstructionSet_POPCNT);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
resultflags.RemoveInstructionSet(InstructionSet_Vector256);
if (resultflags.HasInstructionSet(InstructionSet_AVXVNNI) && !resultflags.HasInstructionSet(InstructionSet_AVX2))
resultflags.RemoveInstructionSet(InstructionSet_AVXVNNI);
#endif // TARGET_AMD64
#ifdef TARGET_X86
if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
Expand All @@ -408,12 +418,18 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_BMI2);
if (resultflags.HasInstructionSet(InstructionSet_FMA) && !resultflags.HasInstructionSet(InstructionSet_AVX))
resultflags.RemoveInstructionSet(InstructionSet_FMA);
if (resultflags.HasInstructionSet(InstructionSet_LZCNT) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
resultflags.RemoveInstructionSet(InstructionSet_LZCNT);
if (resultflags.HasInstructionSet(InstructionSet_PCLMULQDQ) && !resultflags.HasInstructionSet(InstructionSet_SSE2))
resultflags.RemoveInstructionSet(InstructionSet_PCLMULQDQ);
if (resultflags.HasInstructionSet(InstructionSet_POPCNT) && !resultflags.HasInstructionSet(InstructionSet_SSE42))
resultflags.RemoveInstructionSet(InstructionSet_POPCNT);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
resultflags.RemoveInstructionSet(InstructionSet_Vector256);
if (resultflags.HasInstructionSet(InstructionSet_AVXVNNI) && !resultflags.HasInstructionSet(InstructionSet_AVX2))
resultflags.RemoveInstructionSet(InstructionSet_AVXVNNI);
#endif // TARGET_X86

} while (!oldflags.Equals(resultflags));
Expand Down
174 changes: 16 additions & 158 deletions src/coreclr/jit/compiler.cpp
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Expand Up @@ -2240,169 +2240,27 @@ void Compiler::compSetProcessor()

#endif // TARGET_X86

// The VM will set the ISA flags depending on actual hardware support.
// We then select which ISAs to leave enabled based on the JIT config.
// The exception to this is the dummy Vector64/128/256 ISAs, which must be added explicitly.
CORINFO_InstructionSetFlags instructionSetFlags = jitFlags.GetInstructionSetFlags();
opts.compSupportsISA = 0;
opts.compSupportsISAReported = 0;
opts.compSupportsISAExactly = 0;

#ifdef TARGET_XARCH
if (JitConfig.EnableHWIntrinsic())
{
// Dummy ISAs for simplifying the JIT code
instructionSetFlags.AddInstructionSet(InstructionSet_Vector128);
instructionSetFlags.AddInstructionSet(InstructionSet_Vector256);
}

if (!JitConfig.EnableSSE())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE_X64);
#endif
}

if (!JitConfig.EnableSSE2())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE2);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE2_X64);
#endif
}

if (!JitConfig.EnableAES())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_AES);
}

if (!JitConfig.EnablePCLMULQDQ())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_PCLMULQDQ);
}

// We need to additionally check that COMPlus_EnableSSE3_4 is set, as that
// is a prexisting config flag that controls the SSE3+ ISAs
if (!JitConfig.EnableSSE3() || !JitConfig.EnableSSE3_4())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE3);
}

if (!JitConfig.EnableSSSE3())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSSE3);
}

if (!JitConfig.EnableSSE41())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE41);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE41_X64);
#endif
}

if (!JitConfig.EnableSSE42())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE42);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_SSE42_X64);
#endif
}

if (!JitConfig.EnablePOPCNT())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_POPCNT);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_POPCNT_X64);
#endif
}

if (!JitConfig.EnableAVX())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_AVX);
}

if (!JitConfig.EnableFMA())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_FMA);
}

if (!JitConfig.EnableAVX2())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_AVX2);
}

if (!JitConfig.EnableAVXVNNI())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_AVXVNNI);
}
// The VM will set the ISA flags depending on actual hardware support
// and any specified config switches specified by the user. The exception
// here is for certain "artificial ISAs" such as Vector64/128/256 where they
// don't actually exist. The JIT is in charge of adding those and ensuring
// the total sum of flags is still valid.

if (!JitConfig.EnableLZCNT())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_LZCNT);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_LZCNT_X64);
#endif // TARGET_AMD64
}
CORINFO_InstructionSetFlags instructionSetFlags = jitFlags.GetInstructionSetFlags();

if (!JitConfig.EnableBMI1())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_BMI1);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_BMI1_X64);
#endif // TARGET_AMD64
}

if (!JitConfig.EnableBMI2())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_BMI2);
#ifdef TARGET_AMD64
instructionSetFlags.RemoveInstructionSet(InstructionSet_BMI2_X64);
#endif // TARGET_AMD64
}
opts.compSupportsISA = 0;
opts.compSupportsISAReported = 0;
opts.compSupportsISAExactly = 0;

#if defined(TARGET_XARCH)
instructionSetFlags.AddInstructionSet(InstructionSet_Vector128);
instructionSetFlags.AddInstructionSet(InstructionSet_Vector256);
#endif // TARGET_XARCH
#if defined(TARGET_ARM64)
if (JitConfig.EnableHWIntrinsic())
{
// Dummy ISAs for simplifying the JIT code
instructionSetFlags.AddInstructionSet(InstructionSet_Vector64);
instructionSetFlags.AddInstructionSet(InstructionSet_Vector128);
}

if (!JitConfig.EnableArm64Aes())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_Aes);
}

if (!JitConfig.EnableArm64Atomics())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_Atomics);
}

if (!JitConfig.EnableArm64Crc32())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_Crc32);
instructionSetFlags.RemoveInstructionSet(InstructionSet_Crc32_Arm64);
}

if (!JitConfig.EnableArm64Sha1())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_Sha1);
}

if (!JitConfig.EnableArm64Sha256())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_Sha256);
}

if (!JitConfig.EnableArm64AdvSimd())
{
instructionSetFlags.RemoveInstructionSet(InstructionSet_AdvSimd);
instructionSetFlags.RemoveInstructionSet(InstructionSet_AdvSimd_Arm64);
}
#endif
#if defined(TARGET_ARM64)
instructionSetFlags.AddInstructionSet(InstructionSet_Vector64);
instructionSetFlags.AddInstructionSet(InstructionSet_Vector128);
#endif // TARGET_ARM64

instructionSetFlags = EnsureInstructionSetFlagsAreValid(instructionSetFlags);
opts.setSupportedISAs(instructionSetFlags);
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Commenting here because its in compiler.cpp, but further down on https://github.com/dotnet/runtime/blob/main/src/coreclr/jit/compiler.cpp#L5608-L5637, we have some logic for if (!info.compMatchedVM).

It'd be helpful to understand what this means for crossgen/r2r and if its better handled as simply if (info.altJit). In particular we want to support:

  1. The ability to have "correct" instruction sets for the actual target when the VM doesn't match (i.e. cross-compiling for Arm64 on an x64 box; crossgen or otherwise)
  2. To allow for an AltJit to generate disassembly for hardware you don't have (i.e. see and debug Arm.AdvSimd on x64; or even X86.Avx2 on an x64 box that only supports Avx)

Expand Down
15 changes: 8 additions & 7 deletions src/coreclr/jit/compiler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8686,7 +8686,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#error Unsupported platform
#endif // !TARGET_XARCH && !TARGET_ARM64

return compOpportunisticallyDependsOn(minimumIsa) && JitConfig.EnableHWIntrinsic();
return compOpportunisticallyDependsOn(minimumIsa);
#else
return false;
#endif
Expand All @@ -8704,7 +8704,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#error Unsupported platform
#endif // !TARGET_XARCH && !TARGET_ARM64

return compIsaSupportedDebugOnly(minimumIsa) && JitConfig.EnableHWIntrinsic();
return compIsaSupportedDebugOnly(minimumIsa);
#else
return false;
#endif // FEATURE_SIMD
Expand Down Expand Up @@ -9111,7 +9111,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#if defined(TARGET_XARCH)
if (getSIMDSupportLevel() == SIMD_AVX2_Supported)
{
return JitConfig.EnableHWIntrinsic() ? TYP_SIMD32 : TYP_SIMD16;
return TYP_SIMD32;
}
else
{
Expand Down Expand Up @@ -9152,14 +9152,13 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#if defined(TARGET_XARCH)
if (getSIMDSupportLevel() == SIMD_AVX2_Supported)
{
return JitConfig.EnableHWIntrinsic() ? YMM_REGSIZE_BYTES : XMM_REGSIZE_BYTES;
return YMM_REGSIZE_BYTES;
}
else
{
assert(getSIMDSupportLevel() >= SIMD_SSE2_Supported);

// Verify and record that AVX2 isn't supported
compVerifyInstructionSetUnusable(InstructionSet_AVX2);
assert(getSIMDSupportLevel() >= SIMD_SSE2_Supported);
return XMM_REGSIZE_BYTES;
}
#elif defined(TARGET_ARM64)
Expand All @@ -9182,10 +9181,12 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#if defined(FEATURE_HW_INTRINSICS) && defined(TARGET_XARCH)
if (compOpportunisticallyDependsOn(InstructionSet_AVX))
{
return JitConfig.EnableHWIntrinsic() ? YMM_REGSIZE_BYTES : XMM_REGSIZE_BYTES;
return YMM_REGSIZE_BYTES;
}
else
{
// Verify and record that AVX2 isn't supported
compVerifyInstructionSetUnusable(InstructionSet_AVX2);
assert(getSIMDSupportLevel() >= SIMD_SSE2_Supported);
return XMM_REGSIZE_BYTES;
}
Expand Down
15 changes: 3 additions & 12 deletions src/coreclr/jit/ee_il_dll.cpp
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Expand Up @@ -335,20 +335,11 @@ unsigned CILJit::getMaxIntrinsicSIMDVectorLength(CORJIT_FLAGS cpuCompileFlags)
if (!jitFlags.IsSet(JitFlags::JIT_FLAG_PREJIT) && jitFlags.IsSet(JitFlags::JIT_FLAG_FEATURE_SIMD) &&
jitFlags.GetInstructionSetFlags().HasInstructionSet(InstructionSet_AVX2))
{
// Since the ISAs can be disabled individually and since they are hierarchical in nature (that is
// disabling SSE also disables SSE2 through AVX2), we need to check each ISA in the hierarchy to
// ensure that AVX2 is actually supported. Otherwise, we will end up getting asserts downstream.
if ((JitConfig.EnableAVX2() != 0) && (JitConfig.EnableAVX() != 0) && (JitConfig.EnableSSE42() != 0) &&
(JitConfig.EnableSSE41() != 0) && (JitConfig.EnableSSSE3() != 0) && (JitConfig.EnableSSE3_4() != 0) &&
(JitConfig.EnableSSE3() != 0) && (JitConfig.EnableSSE2() != 0) && (JitConfig.EnableSSE() != 0) &&
(JitConfig.EnableHWIntrinsic() != 0))
if (GetJitTls() != nullptr && JitTls::GetCompiler() != nullptr)
{
if (GetJitTls() != nullptr && JitTls::GetCompiler() != nullptr)
{
JITDUMP("getMaxIntrinsicSIMDVectorLength: returning 32\n");
}
return 32;
JITDUMP("getMaxIntrinsicSIMDVectorLength: returning 32\n");
}
return 32;
}
#endif // defined(TARGET_XARCH)
if (GetJitTls() != nullptr && JitTls::GetCompiler() != nullptr)
Expand Down
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