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@kunalspathak kunalspathak commented Jan 13, 2021

As pointed out in my analysis in #46085 (comment), after #45135, we added a DEBUG only validation that checks if a RegRecord doesn't have an assigned interval, it should be free and its entry should be present in m_AvailableRegs mask. However, for ARM, that invariant was not maintained.

In Arm, a pair of registers are used to store value of TYP_DOUBLE. However, if a register pair was previously assigned to an interval that has TYP_DOUBLE value and we are currently trying to assign a register to an interval that has TYP_FLOAT value, we unassign both registers and re-assign one of the register of the pair to the current interval. However, we were not marking the other half register as free. This is done in liveRegs that tracks the live variables. The fix was that whenever we see this happening, remove the other half register from the liveRegs mask, so it is considered as free.

JitStressregs is green. The failures in JitStress2-JitStressRegs are unrelated and are because of the following issues:

Fixes: #46085

@ghost ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jan 13, 2021
@kunalspathak kunalspathak marked this pull request as ready for review January 14, 2021 21:30
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@dotnet/jit-contrib

@JulieLeeMSFT JulieLeeMSFT added this to the 6.0.0 milestone Jan 14, 2021
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Failure in windows arm64 is unrelated. Failure in libraries-jitstressregs is related to #46086

@kunalspathak kunalspathak merged commit 0f86c45 into dotnet:master Jan 20, 2021
kunalspathak added a commit to kunalspathak/runtime that referenced this pull request Feb 2, 2021
@ghost ghost locked as resolved and limited conversation to collaborators Feb 27, 2021
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Assertion failed 'isRegAvailable(reg, physRegRecord->registerType)' in 'testout1:Func_0_5_2_4():float' during 'LSRA build intervals'

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