Arm64: don't fold ldr page offset (PAGEOFFSET_12L) for NativeAOT by EgorBo · Pull Request #129966 · dotnet/runtime

EgorBo · 2026-06-29T06:02:03Z

PR #129589 added an Arm64 fold of adrp+add+ldr into adrp+ldr[#:lo12:] via a 64-bit PAGEOFFSET_12L reloc (R_AARCH64_LDST64_ABS_LO12_NC). That reloc encodes the offset scaled by 8, so the target must be 8-byte aligned. In R2R the relocatable loads always go through pointer-aligned indirection cells, but NativeAOT can fold a direct 64-bit load of byte-packed frozen data (4-byte aligned), which ld.lld rejects:

ld.lld : error : improper alignment for relocation R_AARCH64_LDST64_ABS_LO12_NC: 0x74A52C is not aligned to 8 bytes

The fold is purely a size optimization, so this restricts it to non-NativeAOT and falls back to the always-safe adrp+add+ldr.

Validation (SPMI, linux-arm64):

benchmarks.run (R2R, ~427K contexts): 0 asm diffs — the win is preserved.
smoke_tests.nativeaot (18891 ctx): clean replay, no diffs.

The adrp+add+ldr to adrp+ldr[#:lo12:] fold uses a 64-bit PAGEOFFSET_12L reloc (R_AARCH64_LDST64_ABS_LO12_NC), whose scaled offset requires the target to be 8-byte aligned. R2R loads always go through pointer-aligned indirection cells, but NativeAOT can fold a direct 64-bit load of byte-packed frozen data (4-byte aligned), which the linker rejects with 'improper alignment for relocation'. Restrict the fold to non-NativeAOT. Fixes dotnet#129936 Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

dotnet-policy-service · 2026-06-29T06:03:19Z

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Copilot

Pull request overview

This PR adjusts the Arm64 emitter’s TryFoldPageOffsetIntoLdr peephole optimization to avoid emitting PAGEOFFSET_12L relocations when targeting the NativeAOT ABI, preventing generation of linker-invalid R_AARCH64_LDST64_ABS_LO12_NC relocations in scenarios where the referenced symbol may not be 8-byte aligned.

Changes:

Disable adrp+add+ldr → adrp+ldr[#:lo12:] folding for NativeAOT by early-returning in TryFoldPageOffsetIntoLdr.
Add an in-code rationale describing the alignment requirement of PAGEOFFSET_12L / R_AARCH64_LDST64_ABS_LO12_NC and why NativeAOT differs.

jakobbotsch

LGTM

Co-authored-by: Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>

Copilot

Pull request overview

Copilot reviewed 1 out of 1 changed files in this pull request and generated 1 comment.

jkotas · 2026-07-01T17:13:39Z

        return false;
    }

+    // PAGEOFFSET_12L requires alignment which is not guaranteed for NAOT


Where is it guaranteed for R2R?

@jkotas I'd assumed all relocatable constants in R2R go through (pointer-aligned) indirection slots. I tried to trick it with misaligned reads/writes to RVA data, but RVA blobs are always pointer-aligned too (requiredAlignment = targetPointerSize in GetRvaData). The failing case is actually NAOT statics: NAOT addresses non-GC statics directly and aligns the static region only to the largest static field's alignment (NonGCStaticFieldAlignment), which is 4 here (struct S { uint A, B; }). JIT's Physical promotion then does a 64-bit load of the struct at that 4-aligned address, which we fold into ldr [x],#:lo12: and LDST64_ABS_LO12 can't encode a non-8-aligned offset. R2R only ever directly addresses RVA data (pointer-aligned); regular statics go through helpers, so it's safe there.

If you think this introduces a fragility I can revert it, I just assumed the diffs (e.g. -200kb from corelib's size) was worth it.

A separate question is whether it makes sense to increase alignment for statics to 8 bytes (or even 16) as well for perf since JIT loves to optimize struct loads with wider loads🤔 (to avoid perf penalty from misalignment)

cc @MichalStrehovsky

On coreclr, presumably, all static fields holding structs are pointer-size aligned (boxed objects).

If you think this introduces a fragility

Yes, I think this implementation is fragile. It assumes an invariant that is not guaranteed by the system. I think it is just a matter of time until we run into an invalid reloc with R2R too here. A better way to do this would be to e.g. add JIT/EE interface API that returns the alignment of the blob.

-200kb from corelib's size

I like the code size reduction

it makes sense to increase alignment for statics to 8 bytes

It may help a bit with NAOT statics, but it won't fix the problem for instance fields (for both JIT and AOT). Correct?

The adrp+add+ldr -> adrp+ldr[#:lo12:] fold uses R_AARCH64_LDST64_ABS_LO12_NC, which encodes the :lo12: page offset scaled by 8, so the reloc target must be 8-byte aligned. Replace the blanket NativeAOT opt-out with a new JIT-EE API, getAddressAlignment(void*), and only fold when the VM guarantees the target is at least 8-byte aligned. - VM (CoreCLR/NGen): reports the alignment of the absolute address. - crossgen2 (R2R): reports pointer size; direct relocatable loads only target pointer-aligned data. - NativeAOT: reports the exact alignment of non-GC statics (the failing case) and pointer size for GC-statics/RVA data, and fails closed otherwise so an unaligned relocation can never be emitted. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

MichalStrehovsky

Thank you for making it work for native AOT!

MichalStrehovsky · 2026-07-06T00:37:43Z

+                case NonGCStaticsNode nonGcStatics:
+                    // The non-GC static region is aligned only to the largest static field's
+                    // alignment (plus the cctor-context's pointer alignment when present), which
+                    // can be smaller than the pointer size for byte-packed layouts.
+                    LayoutInt fieldAlignment = nonGcStatics.Type.NonGCStaticFieldAlignment;
+                    int baseAlignment = fieldAlignment.IsIndeterminate ? pointerSize : fieldAlignment.AsInt;
+                    alignment = nonGcStatics.HasCCtorContext ? Math.Max(baseAlignment, pointerSize) : baseAlignment;
+                    break;
+
+                case GCStaticsNode:
+                case FieldRvaDataNode:
+                    // These are laid out with at least pointer-size alignment.
+                    alignment = pointerSize;
+                    break;


Could you add a IObjectNodeWithAlignment interface with a int GetAlignment(NodeFactory factory) method and have these nodes implement it? Then make sure GetAlignment is actually the number that gets reported from GetObjectData/GetDehydratableData. This is duplicating the logic in GetXXXData and runs the risk of getting out of sync.

MichalStrehovsky · 2026-07-06T00:38:23Z

+        private uint getAddressAlignment(void* address)
+        {
+            if (address == null)
+            {
+                return 1;
+            }
+#if READYTORUN
+            // In R2R, relocatable direct loads only target pointer-aligned data (RVA blobs and
+            // indirection cells); statics and other data are reached through helpers. Report
+            // pointer-size alignment, matching how such targets are laid out.
+            return (uint)_compilation.TypeSystemContext.Target.PointerSize;
+#else
+            if (HandleToObject(address) is ISymbolNode node)
+            {
+                return (uint)GetSymbolNodeAlignment(node);
+            }
+
+            // Unknown target: report unaligned so the JIT avoids alignment-sensitive relocations.
+            return 1;
+#endif


If the body is this different, let's put these into CorInfoImpl.ReadyToRun.cs (R2R) and CorInfoImpl.RyuJIT.cs (native AOT) instead and skip the ifdefs.

Copilot AI review requested due to automatic review settings June 29, 2026 06:02

github-actions Bot added the area-NativeAOT-coreclr label Jun 29, 2026

dotnet-policy-service Bot assigned EgorBo Jun 29, 2026

Copilot started reviewing on behalf of EgorBo June 29, 2026 06:02 View session

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MichalStrehovsky mentioned this pull request Jun 29, 2026

Disable System.Text.Json polymorphic source-gen tests on NativeAOT #129965

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Comment thread src/coreclr/jit/emitarm64.cpp Outdated

jakobbotsch approved these changes Jun 29, 2026

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Update src/coreclr/jit/emitarm64.cpp

55a7030

Co-authored-by: Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>

Copilot AI review requested due to automatic review settings July 1, 2026 16:53

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Comment thread src/coreclr/jit/emitarm64.cpp Outdated

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github-actions Bot mentioned this pull request Jul 2, 2026

[aw] No-Op Runs #129501

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EgorBo requested a review from MichalStrehovsky as a code owner July 3, 2026 16:05

build-analysis Bot mentioned this pull request Jul 3, 2026

[ci-scan] Test failure: System.Formats.Tar.Tests.TarFile_ExtractToDirectory_File_Tests.ExtractToDirectory_RejectsChainedSymlinkDirectoryTraversal_WithNestedFile #130177

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Arm64: don't fold ldr page offset (PAGEOFFSET_12L) for NativeAOT#129966

Arm64: don't fold ldr page offset (PAGEOFFSET_12L) for NativeAOT#129966
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EgorBo:fix-129936-arm64-12l-naot

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