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Apply format patch in lsraarm64.cpp #114603

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Merged
merged 1 commit into from
Apr 14, 2025
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Apply format patch in lsraarm64.cpp #114603

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12 changes: 7 additions & 5 deletions src/coreclr/jit/lsraarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1481,14 +1481,16 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, int* pDstCou
{
srcCount += BuildContainedCselUses(containedCselOp, delayFreeOp, candidates);
}
else if ((intrin.category == HW_Category_SIMDByIndexedElement) && (genTypeSize(intrin.baseType) == 2) && !HWIntrinsicInfo::HasImmediateOperand(intrin.id))
else if ((intrin.category == HW_Category_SIMDByIndexedElement) && (genTypeSize(intrin.baseType) == 2) &&
!HWIntrinsicInfo::HasImmediateOperand(intrin.id))
{
// Some "Advanced SIMD scalar x indexed element" and "Advanced SIMD vector x indexed element" instructions (e.g.
// "MLA (by element)") have encoding that restricts what registers that can be used for the indexed element when
// the element size is H (i.e. 2 bytes).
// Some "Advanced SIMD scalar x indexed element" and "Advanced SIMD vector x indexed element" instructions
// (e.g. "MLA (by element)") have encoding that restricts what registers that can be used for the indexed
// element when the element size is H (i.e. 2 bytes).
if (((opNum == 2) || (opNum == 3)))
{
// For those intrinsics, just force the delay-free registers, so they do not conflict with the definition.
// For those intrinsics, just force the delay-free registers, so they do not conflict with the
// definition.
srcCount += BuildDelayFreeUses(operand, nullptr, candidates);
}
else
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