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Don't use ZR as target in LSE atomics #105854
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@AndyAyersMS @dotnet/jit-contrib cc @VSadov PTAL, no diffs. I am not sure LSRA can ever decide to assign a zero reg as target reg so my |
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Seems like we might need more of this elsewhere?
Can you please point me to any? There is one more place with |
I don't know of any -- just that LLVM has relatively large lists for both cases. |
Yeah the list of instructions is big, but we don't use any besides these in my PR. Arm64 has many interesting atomic instructions like "atomic min/max, atomic bit-clear/bit-set" but .NET doesn't have APIs for them/doesn't try to recognize idioms |
Addresses @AndyAyersMS's concerns in #105441 (comment)
TL;DR - some instructions relax their semantics when ZR register is used as target. LLVM avoids that via
atomicBarrierDroppedOnZero
andatomicBarrierDroppedOnZero