Skip to content

ARM64: redundant overflow and divbyzero checks #98100

Closed
@EgorBo

Description

@EgorBo
int Test(int a, int b) => b != 0 ? a / b : 0; // or e.g. "b > 0" etc

Current codegen on ARM64:

; Method Prog:Test(int,int):int:this (FullOpts)
G_M26116_IG01:
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
G_M26116_IG02:
            cbnz    w2, G_M26116_IG05
G_M26116_IG03:
            mov     w0, wzr
G_M26116_IG04:
            ldp     fp, lr, [sp], #0x10
            ret     lr
G_M26116_IG05:
            cmp     w2, #0
            beq     G_M26116_IG08
            cmn     w2, #1
            bne     G_M26116_IG06
            cmp     w1, #1
            bvs     G_M26116_IG09
G_M26116_IG06:
            sdiv    w0, w1, w2
G_M26116_IG07:
            ldp     fp, lr, [sp], #0x10
            ret     lr
G_M26116_IG08:
            bl      CORINFO_HELP_THROWDIVZERO
G_M26116_IG09:
            bl      CORINFO_HELP_OVERFLOW
            brk_windows #0
; Total bytes of code: 72

in this case JIT should be able to remove the CORINFO_HELP_THROWDIVZERO since b is proven to be always != 0.

Metadata

Metadata

Assignees

Labels

arch-arm64area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Type

No type

Projects

No projects

Milestone

Relationships

None yet

Development

No branches or pull requests

Issue actions