Closed
Description
As mentioned in #68822 (comment), if we have checks V12 <= 0 and then V12 < 0, we do not eliminate the later check, even though we could. In below example, we can just see that [001094] does V12 <= 0 and few nodes later, we have [001333] which does V12 < 0 and should just eliminate [001333] because it is already taken care? Currently, since the two operators are different (LE and LT), they get different value numbers and we don't even bother considering them for assertion prop it seems.
***** BB03
STMT00128 ( INL01 @ 0x06B[E-] ... ??? ) <- INLRT @ 0x015[E-]
N004 ( 5, 5) [001093] ------------ * JTRUE void $VN.Void
N003 ( 3, 3) [001094] J------N---- \--* LE int $307
N001 ( 1, 1) [001095] ------------ +--* LCL_VAR int V12 tmp3 u:2 $306
N002 ( 1, 1) [001096] ------------ \--* CNS_INT int 0 $c0
------------ BB04 [???..???), preds={BB03} succs={BB05}
------------ BB05 [???..???) -> BB31 (cond), preds={BB04} succs={BB06,BB31}
***** BB05
STMT00157 ( ??? ... ??? )
N004 ( 5, 5) [001330] ------------ * JTRUE void $VN.Void
N003 ( 3, 3) [001329] J------N---- \--* EQ int $c0
N001 ( 1, 1) [001327] ------------ +--* LCL_VAR ref V05 loc2 u:2 $2c2
N002 ( 1, 1) [001328] ------------ \--* CNS_INT ref null $VN.Null
------------ BB06 [???..???) -> BB31 (cond), preds={BB05} succs={BB07,BB31}
***** BB06
STMT00158 ( ??? ... ??? )
N004 ( 5, 5) [001334] ------------ * JTRUE void $VN.Void
N003 ( 3, 3) [001333] J------N---- \--* LT int $308
N001 ( 1, 1) [001331] ------------ +--* LCL_VAR int V12 tmp3 u:2 $306
N002 ( 1, 1) [001332] ------------ \--* CNS_INT int 0 $c0
------------ BB07 [???..???) -> BB31 (cond), preds={BB06} succs={BB86,BB31}
Because of this, we end up generating:
G_M30617_IG04:
mov r10d, dword ptr [rcx+8]
lea r11d, [r10-1]
test r11d, r11d ; <-- cond1
jle G_M30617_IG24
test r11d, r11d ; <-- same as cond1
jl G_M30617_IG18
cmp r10d, r11d
jl G_M30617_IG18
mov rax, 0xD1FFAB1E
mov rbx, gword ptr [rax]