LoongArch: LSX/LASX usage in CoreCLR

[driver1998]

I am trying to port CoreCLR to the 2K0300 SoC, a LoongArch SoC with no LSX/LASX support.

From what I can see, SIMD JIT codegen is guarded behind FEATURE_SIMD and is not enabled by default, so that's fine.

But context switching code in PAL uses LASX xvld/xvsd instruction to load/save floating point/vector registers without any checks.

See:

runtime/src/coreclr/pal/src/arch/loongarch64/context2.S

Line 41 in a49ed69

xvld $xr0, $a0, CONTEXT_FPU_OFFSET + 0

This breaks on 2K0300, and I think also the 2K1000 / 2K2000 chips that do have LSX but no LASX.

I partially reverted the change (d74b524) and got a ImageSharp / dotnet-iot sample running on the 2K0300. Will still need to figure out a cleaner way to do it, like checking LSX/LASX support in runtime and use the correct instructions in each senario.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[driver1998]

cc @shushanhf @LuckyXu-HF

[shushanhf]

See:

runtime/src/coreclr/pal/src/arch/loongarch64/context2.S

Line 41 in a49ed69

xvld $xr0, $a0, CONTEXT_FPU_OFFSET + 0

Thanks, we will check it.

[xen0n]

Yeah, CPU capabilities should be checked upfront by means of HWCAP.