Closed
Description
❯ DOTNET_TieredCompilation=0 $CORE_ROOT/corerun ./artifacts/tests/coreclr/linux.arm64.Checked/JIT/HardwareIntrinsics/HardwareIntrinsics_Arm_ro/HardwareIntrinsics_Arm_ro.dll Sve_ZeroExtendWideningUpper_ushort_byte
10:19:02.221 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ZeroExtendWideningUpper_ushort_byte()
Supported ISAs:
AdvSimd: True
Aes: True
ArmBase: True
Crc32: True
Dp: True
Rdm: True
Sha1: True
Sha256: True
Sve: True
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_FalseOp_mask - operation in trueValue
Sve.ZeroExtendWideningUpper<UInt16>(Vector<UInt16>, Vector<UInt16>): ConditionalSelectScenario_TrueValue failed:
mask: (0, 1, 0, 0, 1, 0, 0, 1)
firstOp: (71, 101, 222, 120, 16, 10, 142, 49, 101, 241, 40, 202, 214, 146, 214, 57)
falseOp: (25927, 30942, 2576, 12686, 61797, 51752, 37590, 14806)
result: (25927, 241, 2576, 12686, 214, 51752, 37590, 57)
Beginning scenario: ConditionalSelect_FalseOp_zero - operation in trueValue
Beginning scenario: ConditionalSelect_FalseOp_all - operation in trueValue
Sve.ZeroExtendWideningUpper<UInt16>(Vector<UInt16>, Vector<UInt16>): ConditionalSelectScenario_TrueValue failed:
mask: (65535, 65535, 65535, 65535, 65535, 65535, 65535, 65535)
firstOp: (71, 101, 222, 120, 16, 10, 142, 49, 101, 241, 40, 202, 214, 146, 214, 57)
falseOp: (25927, 30942, 2576, 12686, 61797, 51752, 37590, 14806)
result: (101, 241, 40, 202, 214, 146, 214, 57)
Beginning scenario: ConditionalSelect_FalseOp_mask - operation in falseValue
Beginning scenario: ConditionalSelect_FalseOp_zero - operation in falseValue
Beginning scenario: ConditionalSelect_FalseOp_all - operation in falseValue
Beginning scenario: ConditionalSelect_ZeroOp_mask - operation in trueValue
Sve.ZeroExtendWideningUpper<UInt16>(Vector<UInt16>, Vector<UInt16>): ConditionalSelectScenario_TrueValue failed:
mask: (0, 1, 0, 0, 1, 0, 0, 1)
firstOp: (71, 101, 222, 120, 16, 10, 142, 49, 101, 241, 40, 202, 214, 146, 214, 57)
falseOp: (0, 0, 0, 0, 0, 0, 0, 0)
result: (0, 241, 0, 0, 214, 0, 0, 57)
Beginning scenario: ConditionalSelect_ZeroOp_zero - operation in trueValue
Beginning scenario: ConditionalSelect_ZeroOp_all - operation in trueValue
Sve.ZeroExtendWideningUpper<UInt16>(Vector<UInt16>, Vector<UInt16>): ConditionalSelectScenario_TrueValue failed:
mask: (65535, 65535, 65535, 65535, 65535, 65535, 65535, 65535)
firstOp: (71, 101, 222, 120, 16, 10, 142, 49, 101, 241, 40, 202, 214, 146, 214, 57)
falseOp: (0, 0, 0, 0, 0, 0, 0, 0)
result: (101, 241, 40, 202, 214, 146, 214, 57)
Beginning scenario: ConditionalSelect_ZeroOp_mask - operation in falseValue
Beginning scenario: ConditionalSelect_ZeroOp_zero - operation in falseValue
Beginning scenario: ConditionalSelect_ZeroOp_all - operation in falseValue
System.Exception: One or more scenarios did not complete as expected.
at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ZeroExtendWideningUpper_ushort_byte() in /home/alahay01/dotnet/runtime_sve/artifacts/tests/coreclr/obj/linux.arm64.Checked/Managed/JIT/HardwareIntrinsics/Arm/Sve/Sve_ro/Sve_ro/gen/Sve.ZeroExtendWideningUpper.ushort.byte.cs:line 68
at Program.<<Main>$>g__TestExecutor3883|0_3884(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in /home/alahay01/dotnet/runtime_sve/artifacts/tests/coreclr/obj/linux.arm64.Checked/Managed/JIT/HardwareIntrinsics/HardwareIntrinsics_Arm_ro/generated/XUnitWrapperGenerator/XUnitWrapperGenerator.XUnitWrapperGenerator/FullRunner.g.cs:line 97407
10:19:02.987 Failed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ZeroExtendWideningUpper_ushort_byte()
Same issues with other zero/sign extending tests.