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Xinlong-Wuam11
Xinlong-Wu
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am11
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[Mono][RISC-V] Lowering and output more OP for Regression test (#96368)
* opt MUL/DIV lowering logic * update * update * process return type ArgInFRegR4 decompose OP_ICONV_TO_OVF_* lowering & output OP_MOVE_F_TO_I*, OP_MOVE_I*_TO_F, OP_{F|R}C{LE|LT|EQ|NEQ|GT|GE}, OP_LCALL_REG * remove unusable var * Create jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * Update jit-riscv64.yml * dump asm * Update jit-riscv64.yml * tailcall * r4_add * update yml * update yml * update yml * update yml * update yml * OP_LCONV_TO_R4 * update yml * OP_RSUB * remove assert for lowering OP_STORER4_MEMBASE_REG * fix * OP_FBEQ * OP_IMUL_OVF_UN * MONO_TYPE_TYPEDBYREF * float_conv_to_u4 * update yml * OP_ADDCC for OP_COND_EXC_IC * OP_RCONV_TO_R4 * fix * update yml * OP_RCONV_TO_OVF_U8 * lowering OP_RCONV_TO_R4 * OP_LCONV_TO_OVF_I2 * OP_FCONV_TO_U1 * OP_LCONV_TO_OVF_I8 * OP_RNEG * OP_LSHR * OP_{F|R}CONV_TO_U* * OP_CKFINITE * update yml * update yml * OP_FCONV_TO_U8 * rcall_reg * remove assert of OP_TAILCALL * OP_ICONV_TO_OVF_I * OP_LSUB_OVF_UN * OP_FBNE_UN after OP_RCOMPARE * fix * update ymal * fix rd for lowering OP_RCOMPARE * decompose the OP long_conv_to_i1 * update yml * tailcall_reg * r4_conv_to_u4 * process OP_COND_EXC_NC after OP_LSUBCC * update yml * OP_FCONV_TO_U8 * OP_ICONV_TO_OVF_I4_UN * OP_FREM * OP_RREM * OP_FCONV_TO_U8, OP_FCONV_TO_OVF_U8 * update test Script * Update jit-riscv64.yml * Update jit-riscv64.yml * update test Script * clean yml * update yml * OP_LCONV_TO_OVF_I_UN * OP_COND_EXC_C * loadr8_membase * OP_RCONV_TO_U2 * case OP_RCONV_TO_U4: * fix compile error * use next_inst instead of ins->next * update * OP_COND_EXC_IC * int_xor_imm * r4_conv_to_u8 * trace_diff.py * set RISCV_ROUND_TZ for OP_{R|F}CONV_TO_ * update * emit OP_LSUB when OP_SUBCC * output OP_FCONV_TO_U8 * long_xor_imm * move throw ip to RISCV_RA from RISCV_T0 * fix Div By Zero check of OP_{F|R}DIV * OP_{F|R}MOVE * lowering _IMM to _REG * OP_ATOMIC LOAD & STORE * extend thunk size when mono_riscv_emit_branch_exc remove Devide by Zero check for {F|R}_DIV * fix lowering OP_INEG/OP_LNEG * lowering OP_IADD_IMM or OP_LADD_IMM by OP_ICEQ or OP_LCEQ * casting return value to uint8 * for test * define MONO_ARCH_LLVM_SUPPORTED to insert extra truncate inst * reset test case * fix case OP_COND_EXC_C after OP_ADDCC * use OP_RISCV_R|F BNAN help for R|F compare * dont emit OP_RISCV_RBNAN for FBEQ&FBNE * process all unorder operattions * use MicroDef MONO_ARCH_EXC_ADDR_REG for throw exception * make pc point to EXC_BRANCH inst * fix length of ckfinite * fix OP_I8const and OP_ICONST * fix icompare * fix OP_COND_EXC_IC for SUBCC * skip test of gc_poll * process OP_BR after OP_FCOMPARE * skip gc_poll test * tmp * clean the code * clean * clang format file * fmt * remove format file * Update issues.targets * Update src/mono/mono/mini/mini-ops.h Co-authored-by: Adeel Mujahid <3840695+am11@users.noreply.github.com> * fix compile error * Update mini-riscv.c --------- Co-authored-by: Adeel Mujahid <3840695+am11@users.noreply.github.com>
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‎src/mono/mono/arch/riscv/riscv-codegen.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,21 @@ enum {
252252
RISCV_ROUND_DY = 0b111, // Use current rounding mode in the FRM CSR.
253253
};
254254

255+
enum {
256+
RISCV_FCLASS_NINF = 0b1 << 0, // Negative infinity.
257+
RISCV_FCLASS_NN = 0b1 << 1, // Negative normal.
258+
RISCV_FCLASS_ND = 0b1 << 2, // Negative denormal.
259+
RISCV_FCLASS_NZ = 0b1 << 3, // Negative zero.
260+
RISCV_FCLASS_PZ = 0b1 << 4, // Positive zero.
261+
RISCV_FCLASS_PD = 0b1 << 5, // Positive denormal.
262+
RISCV_FCLASS_PN = 0b1 << 6, // Positive normal.
263+
RISCV_FCLASS_PINF = 0b1 << 7, // Positive infinity.
264+
RISCV_FCLASS_SNAN = 0b1 << 8, // Signalling NaN.
265+
RISCV_FCLASS_QNAN = 0b1 << 9, // Quiet NaN.
266+
RISCV_FCLASS_INF = RISCV_FCLASS_NINF | RISCV_FCLASS_PINF,
267+
RISCV_FCLASS_NAN = RISCV_FCLASS_SNAN | RISCV_FCLASS_QNAN,
268+
};
269+
255270
#define _riscv_emit(p, insn) \
256271
do { \
257272
*(guint32 *) (p) = (insn); \

‎src/mono/mono/mini/cpu-riscv64.mdesc

Lines changed: 67 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ endfilter: src1:i len:32
4545
localloc: dest:i src1:i len:52
4646
localloc_imm: dest:i len:28
4747
generic_class_init: src1:a len:12 clob:c
48+
ckfinite: dest:f src1:f len:28
4849
break: len:4
4950

5051
throw: src1:i len:4
@@ -63,23 +64,30 @@ vcall2: len:16 clob:c
6364
vcall2_reg: src1:i len:16 clob:c
6465
vcall2_membase: src1:b len:28 clob:c
6566
fcall: dest:f len:8 clob:c
66-
rcall: dest:f len:8 clob:c
67-
rcall_membase: dest:f src1:b len:12 clob:c
6867
fcall_reg: dest:f src1:i len:8 clob:c
6968
fcall_membase: dest:f src1:b len:12 clob:c
69+
rcall: dest:f len:8 clob:c
70+
rcall_reg: dest:f src1:i len:8 clob:c
71+
rcall_membase: dest:f src1:b len:12 clob:c
7072

7173
# Note: in RV32, it shoule be
7274
# lcall: dest:l ...
7375
lcall: dest:a len:16 clob:c
76+
lcall_reg: dest:a src1:i len:4 clob:c
7477
lcall_membase: dest:a src1:b len:8 clob:c
7578

79+
tailcall_parameter: len:24
80+
tailcall: len:60 clob:c
81+
tailcall_membase: src1:b len:60 clob:c
82+
tailcall_reg: src1:b len:60 clob:c
83+
7684
store_membase_reg: dest:b src1:i len:24
7785
storei1_membase_reg: dest:b src1:i len:24
7886
storei2_membase_reg: dest:b src1:i len:24
7987
storei4_membase_reg: dest:b src1:i len:24
8088
storei8_membase_reg: dest:b src1:i len:24
81-
storer4_membase_reg: dest:b src1:f len:4
82-
storer8_membase_reg: dest:b src1:f len:4
89+
storer4_membase_reg: dest:b src1:f len:24
90+
storer8_membase_reg: dest:b src1:f len:24
8391

8492
load_membase: dest:i src1:b len:24
8593
loadu1_membase: dest:i src1:b len:24
@@ -89,18 +97,26 @@ loadi2_membase: dest:i src1:b len:24
8997
loadu4_membase: dest:i src1:b len:24
9098
loadi4_membase: dest:i src1:b len:24
9199
loadi8_membase: dest:i src1:b len:24
92-
loadr4_membase: dest:f src1:b len:16
93-
loadr8_membase: dest:f src1:b len:16
100+
loadr4_membase: dest:f src1:b len:24
101+
loadr8_membase: dest:f src1:b len:24
94102

95103
memory_barrier: len:4
96104
atomic_add_i4: dest:i src1:i src2:i len:4
97105
atomic_add_i8: dest:i src1:i src2:i len:4
106+
atomic_store_i1: dest:b src1:i len:8
98107
atomic_store_u1: dest:b src1:i len:8
108+
atomic_store_i2: dest:b src1:i len:8
109+
atomic_store_u2: dest:b src1:i len:8
99110
atomic_store_i4: dest:b src1:i len:8
100-
atomic_store_u8: dest:b src1:i len:8
111+
atomic_store_u4: dest:b src1:i len:8
101112
atomic_store_i8: dest:b src1:i len:8
113+
atomic_store_u8: dest:b src1:i len:8
114+
atomic_load_i1: dest:b src1:i len:12
102115
atomic_load_u1: dest:b src1:i len:12
116+
atomic_load_i2: dest:b src1:i len:12
117+
atomic_load_u2: dest:b src1:i len:12
103118
atomic_load_i4: dest:b src1:i len:12
119+
atomic_load_u4: dest:b src1:i len:12
104120
atomic_load_i8: dest:b src1:i len:12
105121
atomic_load_u8: dest:b src1:i len:12
106122
atomic_cas_i4: dest:i src1:i src2:i src3:i len:24
@@ -112,48 +128,65 @@ move: dest:i src1:i len:4
112128
lmove: dest:i src1:i len:4
113129
fmove: dest:f src1:f len:4
114130
rmove: dest:f src1:f len:4
131+
move_f_to_i4: dest:i src1:f len:4
132+
move_i4_to_f: dest:f src1:i len:4
133+
move_f_to_i8: dest:i src1:f len:4
134+
move_i8_to_f: dest:f src1:i len:4
115135

116136
iconst: dest:i len:16
117-
i8const: dest:i len:16
118137
int_add: dest:i src1:i src2:i len:4
119-
long_add: dest:i src1:i src2:i len:4
120-
float_add: dest:f src1:f src2:f len:4
121138
int_sub: dest:i src1:i src2:i len:4
122-
long_sub: dest:i src1:i src2:i len:4
123-
float_sub: dest:f src1:f src2:f len:4
124-
float_neg: dest:f src1:f len:4
125139
int_mul: dest:i src1:i src2:i len:4
126-
r4_mul: dest:f src1:f src2:f len:4
127-
long_mul: dest:i src1:i src2:i len:4
128-
float_mul: dest:f src1:f src2:f len:4
129140
int_div: dest:i src1:i src2:i len:32
130-
long_div: dest:i src1:i src2:i len:32
131141
int_div_un: dest:i src1:i src2:i len:32
132-
long_div_un: dest:i src1:i src2:i len:32
133-
r4_div: dest:f src1:f src2:f len:36
134-
float_div: dest:f src1:f src2:f len:36
135142
int_rem: dest:i src1:i src2:i len:32
136-
long_rem: dest:i src1:i src2:i len:32
137143
int_rem_un: dest:i src1:i src2:i len:32
144+
145+
i8const: dest:i len:16
146+
long_add: dest:i src1:i src2:i len:4
147+
long_sub: dest:i src1:i src2:i len:4
148+
long_mul: dest:i src1:i src2:i len:4
149+
long_div: dest:i src1:i src2:i len:32
150+
long_div_un: dest:i src1:i src2:i len:32
151+
long_rem: dest:i src1:i src2:i len:32
138152
long_rem_un: dest:i src1:i src2:i len:32
139153

140-
r4const: dest:f len:16
141154
r8const: dest:f len:16
155+
float_neg: dest:f src1:f len:4
156+
float_add: dest:f src1:f src2:f len:4
157+
float_sub: dest:f src1:f src2:f len:4
158+
float_mul: dest:f src1:f src2:f len:4
159+
float_div: dest:f src1:f src2:f len:36
160+
161+
r4const: dest:f len:16
162+
r4_neg: dest:f src1:f len:4
163+
r4_add: dest:f src1:f src2:f len:4
164+
r4_sub: dest:f src1:f src2:f len:4
165+
r4_mul: dest:f src1:f src2:f len:4
166+
r4_div: dest:f src1:f src2:f len:36
167+
168+
142169
int_conv_to_r4: dest:f src1:i len:4
143170
int_conv_to_r8: dest:f src1:i len:4
144171
r4_conv_to_i8: dest:i src1:f len:4
145172
r4_conv_to_r8: dest:f src1:f len:4
146173
r4_conv_to_i4: dest:i src1:f len:4
174+
r4_conv_to_u4: dest:i src1:f len:4
175+
r4_conv_to_u8: dest:i src1:f len:4
147176
float_conv_to_i4: dest:i src1:f len:4
177+
float_conv_to_u4: dest:i src1:f len:4
148178
float_conv_to_r4: dest:f src1:f len:4
149179
float_conv_to_i8: dest:i src1:f len:4
180+
float_conv_to_u8: dest:i src1:f len:4
181+
182+
r4_ceq: dest:i src1:f src2:f len:4
183+
r4_clt: dest:i src1:f src2:f len:4
184+
r4_clt_un: dest:i src1:f src2:f len:4
185+
r4_cle: dest:i src1:f src2:f len:4
150186
float_ceq: dest:i src1:f src2:f len:4
151187
float_cle: dest:i src1:f src2:f len:4
152188
float_clt: dest:i src1:f src2:f len:4
153189
float_clt_un: dest:i src1:f src2:f len:4
154-
r4_clt: dest:i src1:f src2:f len:4
155-
r4_clt_un: dest:i src1:f src2:f len:4
156-
r4_cle: dest:i src1:f src2:f len:4
157190

158191
add_imm: dest:i src1:i len:4
159192
int_add_imm: dest:i src1:i len:4
@@ -182,27 +215,31 @@ long_and: dest:i src1:i src2:i len:4
182215
long_and_imm: dest:i src1:i len:4
183216
long_or: dest:i src1:i src2:i len:4
184217
long_xor: dest:i src1:i src2:i len:4
218+
long_xor_imm: dest:i src1:i len:4
185219
long_or_imm: dest:i src1:i len:4
186220
long_shl: dest:i src1:i src2:i len:4
187221
long_shl_imm: dest:i src1:i len:4
222+
long_shr: dest:i src1:i src2:i len:4
188223
long_shr_un: dest:i src1:i src2:i len:4
189224
long_shr_imm: dest:i src1:i len:4
190225
long_shr_un_imm: dest:i src1:i len:4
191226

192227

193228
riscv_setfreg_r4: dest:f src1:f len:4
229+
riscv_float_bnan: src1:f len:16
230+
riscv_r4_bnan: src1:f len:16
194231

195232
riscv_beq: src1:i src2:i len:8
196233
riscv_bne: src1:i src2:i len:8
197234
riscv_bge: src1:i src2:i len:8
198235
riscv_bgeu: src1:i src2:i len:8
199236
riscv_blt: src1:i src2:i len:8
200237
riscv_bltu: src1:i src2:i len:8
201-
riscv_exc_beq: src1:i src2:i len:12
202-
riscv_exc_bne: src1:i src2:i len:12
203-
riscv_exc_bgeu: src1:i src2:i len:12
204-
riscv_exc_blt: src1:i src2:i len:12
205-
riscv_exc_bltu: src1:i src2:i len:12
238+
riscv_exc_beq: src1:i src2:i len:16
239+
riscv_exc_bne: src1:i src2:i len:16
240+
riscv_exc_bgeu: src1:i src2:i len:16
241+
riscv_exc_blt: src1:i src2:i len:16
242+
riscv_exc_bltu: src1:i src2:i len:16
206243
riscv_slt: dest:i src1:i src2:i len:4
207244
riscv_sltu: dest:i src1:i src2:i len:4
208245
riscv_slti: dest:i src1:i len:4

‎src/mono/mono/mini/exceptions-riscv.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ mono_riscv_throw_exception (gpointer arg, host_mgreg_t pc, host_mgreg_t *int_reg
8383
}
8484

8585
/* Adjust pc so it points into the call instruction */
86-
pc -= 4;
86+
pc--;
8787

8888
/* Initialize a ctx based on the arguments */
8989
memset (&ctx, 0, sizeof (MonoContext));
@@ -114,7 +114,7 @@ mono_arch_get_call_filter (MonoTrampInfo **info, gboolean aot)
114114
{
115115
guint8 *code;
116116
guint8 *start;
117-
int i, size, offset, gregs_offset, fregs_offset, ctx_offset, num_fregs, frame_size;
117+
int size, offset, gregs_offset, fregs_offset, ctx_offset, frame_size;
118118
MonoJumpInfo *ji = NULL;
119119
GSList *unwind_ops = NULL;
120120

‎src/mono/mono/mini/mini-ops.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1889,6 +1889,8 @@ MINI_OP(OP_RISCV_BGE, "riscv_bge", NONE, IREG, IREG)
18891889
MINI_OP(OP_RISCV_BGEU, "riscv_bgeu", NONE, IREG, IREG)
18901890
MINI_OP(OP_RISCV_BLT, "riscv_blt", NONE, IREG, IREG)
18911891
MINI_OP(OP_RISCV_BLTU, "riscv_bltu", NONE, IREG, IREG)
1892+
MINI_OP(OP_RISCV_RBNAN, "riscv_r4_bnan", NONE, FREG, NONE)
1893+
MINI_OP(OP_RISCV_FBNAN, "riscv_float_bnan", NONE, FREG, NONE)
18921894

18931895
MINI_OP(OP_RISCV_ADDIW, "riscv_addiw", IREG, IREG, NONE)
18941896

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