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A hands-on introduction to Verilog, a hardware description language. It's packed with code examples covering everything from basic logic gates and counters to complex designs like finite state machines (for elevators and railway crossings), various memory types (asynchronous, synchronous, dual-port), and even PRBS generators and FIFOs.

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Name		Name	Last commit message	Last commit date
Latest commit History 31 Commits
Asynchronous Memory		Asynchronous Memory
Basic Logical Elements		Basic Logical Elements
Behavioral Counter		Behavioral Counter
Counter via Full Adder		Counter via Full Adder
Decoder		Decoder
Elevator (FSM)		Elevator (FSM)
Encoder		Encoder
Finite State Machine		Finite State Machine
Full Adder		Full Adder
PRBS Generator + Seed		PRBS Generator + Seed
PRBS Generator		PRBS Generator
Pipeline		Pipeline
Quad Instance Memory		Quad Instance Memory
Railway Crossing (FSM)		Railway Crossing (FSM)
Sync Bitwise Logic AND Gate		Sync Bitwise Logic AND Gate
Synchronous Dual Port Memory		Synchronous Dual Port Memory
Synchronous FIFO (extra bit)		Synchronous FIFO (extra bit)
Synchronous FIFO (extra reg)		Synchronous FIFO (extra reg)
Synchronous Memory - Behavioral		Synchronous Memory - Behavioral
README.md		README.md

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Intro-to-Verilog

EDA Playground Links:

AND Gate: https://www.edaplayground.com/x/BnzQ
OR Gate: https://www.edaplayground.com/x/cG9z
XOR Gate: https://www.edaplayground.com/x/FjZK
NOT Gate: https://www.edaplayground.com/x/dLhk

4'b Synchronous Bitwise Logic AND Gate: https://www.edaplayground.com/x/Bp_H

Full Adder: https://www.edaplayground.com/x/rsmW
Encoder: https://www.edaplayground.com/x/6fUd
Decoder: https://www.edaplayground.com/x/NGzP
Behavioral Counter: https://www.edaplayground.com/x/JYc8
4'b Counter via Full Adder: https://www.edaplayground.com/x/8qbB

PRBS Generator: https://www.edaplayground.com/x/pbpd
PRBS Generator + Seed: https://www.edaplayground.com/x/aARR

Asynchronous Memory: https://www.edaplayground.com/x/BpRK
Synchronous Memory (Behavioral): https://www.edaplayground.com/x/FyBc
Synchronous Dual Port Memory: https://www.edaplayground.com/x/dwt8
Quad Instance Memory: https://www.edaplayground.com/x/V9_H

Finite State Machine: https://www.edaplayground.com/x/J8JA
Elevator (FSM): https://www.edaplayground.com/x/QGzp
Railway Crossing (FSM): https://www.edaplayground.com/x/nQvd

Pipeline: https://www.edaplayground.com/x/jVmH

Synchronous FIFO (extra reg): https://www.edaplayground.com/x/pVUQ
Synchronous FIFO (extra bit): https://www.edaplayground.com/x/95v9

FIFO Verification Environment & Coverage: https://www.edaplayground.com/x/KKgk

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A hands-on introduction to Verilog, a hardware description language. It's packed with code examples covering everything from basic logic gates and counters to complex designs like finite state machines (for elevators and railway crossings), various memory types (asynchronous, synchronous, dual-port), and even PRBS generators and FIFOs.

verilog fifo prbs-generator finate-state-machine memory-type

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