memory_verilog

This is a complete memory design and it's verification using the testbench

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
README.md		README.md
bd_data_write.h		bd_data_write.h
design_memory.v		design_memory.v
run.do		run.do
tb1_memory.v		tb1_memory.v
tb2_memory.v		tb2_memory.v

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