Added flag to enable/disable regular expression matching on Part pin …

…names.

setup.py

@@ -5,7 +5,7 @@
 
 import setuptools
 
-__version__ = "0.0.30"
+__version__ = "0.0.31dev"
 __author__ = "XESS Corp."
 __email__ = "info@xess.com"
 

skidl/Part.py

@@ -174,6 +174,7 @@ def __init__(
         self.tool = tool  # Initial type of part (SKIDL, KICAD, etc.)
         self.circuit = None  # Part starts off unassociated with any circuit.
         self.match_pin_substring = False  # Only select pins with exact name matches.
+        self.match_pin_regex = False  # Don't allow regex matches of pin names.
 
         # Create a Part from a library entry.
         if lib:
@@ -590,12 +591,16 @@ def get_pins(self, *pin_ids, **criteria):
         match_substring = (
             criteria.pop("match_substring", False) or self.match_pin_substring
         )
+        match_regex = (
+            criteria.pop("match_regex", False) or self.match_pin_regex
+        )
 
         # If no pin identifiers were given, then use a wildcard that will
         # select all pins.
         if not pin_ids:
             pin_ids = [".*"]
-            match_substring = ".*"  # Also turn on pin substring matching so .* works.
+            match_substring = True  # Also turn on pin substring matching so .* works.
+            match_regex = True
 
         # Determine the minimum and maximum pin ids if they don't already exist.
         if "min_pin" not in dir(self) or "max_pin" not in dir(self):
@@ -638,6 +643,10 @@ def get_pins(self, *pin_ids, **criteria):
                     pins.extend(tmp_pins)
                     continue
 
+                # Skip matching for substrings or using regex if they're not enabled.
+                if not match_substring and not match_regex:
+                    continue
+
                 # If matching a substring within a pin name is enabled, then
                 # create wildcards to match the beginning/ending surrounding a
                 # substring. Remove these wildcards if substring matching is disabled.
@@ -647,7 +656,8 @@ def get_pins(self, *pin_ids, **criteria):
                 # name or alias. Does it match a substring within a pin name?
                 # Or does it match as a regex?
                 try:
-                    p_id_re = "".join([wildcard, p_id, wildcard])
+                    p_id_re = p_id if match_regex else re.escape(p_id)
+                    p_id_re = "".join([wildcard, p_id_re, wildcard])
                 except TypeError:
                     # This will happen if the p_id is a number and not a string.
                     # Skip this and the next block because p_id_re can't be made.
@@ -668,6 +678,7 @@ def get_pins(self, *pin_ids, **criteria):
 
         return list_or_scalar(pins)
 
+
     # Get pins from a part using brackets, e.g. [1,5:9,'A[0-9]+'].
     __getitem__ = get_pins
 

tests/test_alias.py

@@ -7,6 +7,7 @@
 
 def test_alias_1():
     vreg = Part("xess.lib", "1117")
+    vreg.match_pin_regex = True
     vreg.set_pin_alias("my_alias", 1)
     vreg.set_pin_alias("my_alias", 2)
     assert len(vreg["my_alias"]) == 2
@@ -23,6 +24,7 @@ def test_alias_2():
 
 def test_alias_3():
     vreg = Part("xess.lib", "1117")
+    vreg.match_pin_regex = True
     vreg[1].aliases = "my_alias"
     vreg[2].aliases = "my_alias"
     vreg[2].aliases += "my_other_alias"

tests/test_index_slicing.py

@@ -8,6 +8,7 @@
 def test_index_slicing_1():
     mcu = Part("GameteSnapEDA", "STM32F767ZGT6")
     mcu.match_pin_substring = True
+    mcu.match_pin_regex = True
     assert len(mcu[r"\(FMC_D[0:15]\)"]) == 16
     assert len(mcu[r"\(FMC_D[15:0]\)"]) == 16
     assert len(mcu[r"FMC_D[0:15]\)"]) == 16
@@ -19,6 +20,7 @@ def test_index_slicing_1():
 def test_index_slicing_2():
     mem = Part("GameteSnapEDA", "MT48LC16M16A2TG-6A_IT:GTR")
     mem.match_pin_substring = True
+    mem.match_pin_regex = True
     assert len(mem["DQ[0:15]"]) == 16
     assert len(mem["DQ[15:0]"]) == 16
     assert len(mem["A[0:15]"]) == 13
@@ -29,6 +31,7 @@ def test_index_slicing_2():
 def test_index_slicing_3():
     mem = Part("xess", "SDRAM_16Mx16_TSOPII-54")
     mem.match_pin_substring = True
+    mem.match_pin_regex = True
     assert len(mem["DQ[0:15]"]) == 16
     assert len(mem["DQ[15:0]"]) == 16
     assert len(mem["A[0:15]"]) == 13

tests/test_part_units.py

@@ -9,6 +9,7 @@
 
 def test_part_unit_1():
     vreg = Part("xess.lib", "1117")
+    vreg.match_pin_regex = True
     vreg.make_unit("A", 1, 2)
     vreg.make_unit("B", 3)
     vreg.A.match_pin_substring = True
@@ -19,6 +20,7 @@ def test_part_unit_1():
 
 def test_part_unit_2():
     vreg = Part("xess.lib", "1117")
+    vreg.match_pin_regex = True
     vreg.make_unit("A", 1, 2)
     vreg.make_unit("A", 3)
     assert len((vreg.unit["A"][".*"],)) == 1