CMSIS-Core : Add support for __SXTAB16_RORn

Targetted optimization for GCC when __SXTAB is used with __ROR. Updated description for __SXTB16_RORn Change-Id: I7fbb9afb0a2d5a2f2b239d27af7177a1607ac9a1 Fix review comment: Update description
davemgreen · Feb 23, 2021 · 19b37fe · 19b37fe
1 parent 9f52415
commit 19b37fe
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Showing 7 changed files with 665 additions and 588 deletions.
diff --git a/CMSIS/Core/Include/cmsis_armcc.h b/CMSIS/Core/Include/cmsis_armcc.h
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.2.1
- * @date     26. March 2020
+ * @version  V5.3.0
+ * @date     19. February 2021
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -63,9 +63,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   static __forceinline
-#endif           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __declspec(noreturn)
 #endif
@@ -461,7 +461,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  */
 #define __DMB()                           __dmb(0xF)
 
-                  
+
 /**
   \brief   Reverse byte order (32 bit)
   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
@@ -878,6 +878,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
 
 #define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
 
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /*@} end of group CMSIS_SIMD_intrinsics */
 

diff --git a/CMSIS/Core/Include/cmsis_armclang.h b/CMSIS/Core/Include/cmsis_armclang.h
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armclang.h
  * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V5.3.2
- * @date     16. December 2020
+ * @version  V5.4.0
+ * @date     19. February 2020
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -617,7 +617,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -665,7 +665,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -1248,7 +1248,7 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 #if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
      (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
      (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
-           
+
 /**
   \brief   Load-Acquire (8 bit)
   \details Executes a LDAB instruction for 8 bit value.
@@ -1472,6 +1472,8 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 
 #define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
 
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
 {
   int32_t result;

diff --git a/CMSIS/Core/Include/cmsis_armclang_ltm.h b/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_armclang_ltm.h
  * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V1.4.0
- * @date     29. January 2021
+ * @version  V1.5.0
+ * @date     19. February 2021
  ******************************************************************************/
 /*
  * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -614,7 +614,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -660,7 +660,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -1897,6 +1897,8 @@ __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
 
 #define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
 
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
 {
   int32_t result;

diff --git a/CMSIS/Core/Include/cmsis_gcc.h b/CMSIS/Core/Include/cmsis_gcc.h
@@ -2003,6 +2003,18 @@ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
   return(result);
 }
 
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+  uint32_t result;
+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+    __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
+  } else {
+    result = __SXTAB16(op1, __ROR(op2, rotate));
+  }
+  return result;
+}
+
+
 __STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
 {
   uint32_t result;

diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h
@@ -966,4 +966,6 @@ __packed struct  __iar_u32 { uint32_t v; };
 
 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
 
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 #endif /* __CMSIS_ICCARM_H__ */
diff --git a/CMSIS/CoreValidation/Source/CV_CoreSimd.c b/CMSIS/CoreValidation/Source/CV_CoreSimd.c
@@ -85,6 +85,7 @@ void TC_CoreSimd_ParSat16 (void) {
   __SXTB16
   __SXTB16_RORn
   __SXTAB16
+  __SXTAB16__RORn
   __UXTB16
   __UXTAB16
 */
@@ -114,18 +115,42 @@ void TC_CoreSimd_PackUnpack (void) {
   res_s32 = __SXTB16_RORn(op1_s32, 24);
   ASSERT_TRUE(res_s32 == (int32_t)0x1FF80);
 
-  /* --- __SXTAB16 Test ---------------------------------------------- */
+  /* --- __SXTAB16 Test --------------------------------------------- */
   op1_s32 = (int32_t)0x000D0008;
   op2_s32 = (int32_t)0x80830168;
   res_s32 = __SXTAB16(op1_s32, op2_s32);
   ASSERT_TRUE(res_s32 == (int32_t)0xFF900070);
 
+  /* --- __SXTAB16__ROR8 Test --------------------------------------- */
+  op1_s32 = (int32_t)0x000A000A;
+  op2_s32 = (int32_t)0x80830168;
+  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
+  ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B);
+
+  /* --- __SXTAB16__ROR8 Test --------------------------------------- */
+  op1_s32 = (int32_t)0xFFF6FFF6;
+  op2_s32 = (int32_t)0x80830168;
+  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
+  ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7);
+
+  /* --- __SXTAB16__ROR16 Test -------------------------------------- */
+  op1_s32 = (int32_t)0xFFF60015;
+  op2_s32 = (int32_t)0x70880168;
+  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16);
+  ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D);
+
+  /* --- __SXTAB16__ROR24 Test -------------------------------------- */
+  op1_s32 = (int32_t)0xFFF60015;
+  op2_s32 = (int32_t)0x70880168;
+  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24);
+  ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085);
+
   /* --- __UXTB16 Test ---------------------------------------------- */
   op1_s32 = (int32_t)0x80830168;
   res_s32 = __UXTB16(op1_s32);
   ASSERT_TRUE(res_s32 == 0x00830068);
 
-  /* --- __UXTAB16 Test ---------------------------------------------- */
+  /* --- __UXTAB16 Test --------------------------------------------- */
   op1_s32 =          0x000D0008;
   op2_s32 = (int32_t)0x80830168;
   res_s32 = __UXTAB16(op1_s32, op2_s32);
Original file line number	Diff line number	Diff line change
Expand Up		@@ -966,4 +966,6 @@ __packed struct __iar_u32 { uint32_t v; };

		#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))

		#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))

		#endif /* __CMSIS_ICCARM_H__ */