6.0 r2pro pcie #17
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6.0 r2pro pcie #17
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Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- v4: - add reviewed-by - remove minitems for clock-names as i have static list to fix error - fix reg error by using 32-bit adressing in binding example - change lane-map to u32 data-lanes - tried to move data-lanes to phy-provider https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17 cloned and installed via pip install -e <local path> verified with pip show, but phy-privider seems not to be applied v3: - drop quotes - drop rk3588 - make clockcount fixed to 3 - full path for binding header file - drop phy-mode and its header and add lane-map v2: dt-bindings: rename yaml for PCIe v3 rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml changes in pcie3 phy yaml - change clock names to ordered const list - extend pcie30-phymode description - add phy-cells to required properties - drop unevaluatedProperties - example with 1 clock each line - use default property instead of text describing it - update license
Add compatibles for PCIe v3 General Register Files. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- v4: - rebase on 5.19-rc1 - add acked-by v3: - fix order of grf-bindings v2: - add soc-part to pcie3-phy-grf
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
It use a dedicated PCIe-phy. Add support for this.
Initial support by Shawn Lin, modifications by Peter Geis and Frank
Wunderlich.
Add data-lanes property for splitting pcie-lanes across controllers.
The data-lanes is an array where x=0 means lane is disabled and x > 0
means controller x is assigned to phy lane.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Suggested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v4:
- change u8 lane-map to u32 data-lanes
v3:
- change dt-binding include
- change reset to devm_reset_control_get_optional_exclusive
exit on error and lower severity of message if unset
- fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe
- move bifurcation/lane-map support from PCIe to phy driver
v2:
- move dt-bindings header into separate patch
- use BIT-macro
- make constants better readable
- use dev_err instead of pr_*
- change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h)
- use exclusive variant of devm_reset_control_get{,_exclusive}
- fix semicolon.cocci warnings reported by kernel test robot <lkp@intel.com>
---
driver was taken from linux 5.10 based on in
https://github.com/JeffyCN/mirrors
which now has disappeared
Update phy-rockchip-snps-pcie3.c
Fix messages for data-lanes
Update phy-rockchip-snps-pcie3.c
Fix comment for data-lanes
Add nodes to rk356x devicetree to support PCIe v3. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v4: - update pcie3 reg/ranges v3: - fix from Peter: change bus-range and msi-map, msi-map needs to start from 0x0 v2: - change to compatible with soc-part - change rockchip,bifurcation to vendor unspecific bifurcation
Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and set PCIe related regulators to always on. Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v5: - rebase on 5.19.0 v4: - change u8 lane-map to u32 data-lanes v3: - squash lane-map over bifurcation property - add comment which slot is M2 and which one if mPCIe - fixes from Peter: - drop regulator-always-on/regulator-boot-on from regulators - increase startup-delay-us for regulators - set phy-mode on PCIe3-phy - add num-lanes to PCIe overrides - add usb node for to PCIe/m2 - move lane-map from PCIe controller to PCIe-phy v2: - underscores in nodenames - rockchip,bifurcation to vendor unspecific bifurcation - fix trailing space
PCIe v3 requires ITS for working properly. Add its node. Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Pull PCIE support |
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Pull PCIE support