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Welcome to the CVC wiki!

CVC (Circuit Validity Checker) is a program that checks a netlist for problems in circuit design.

Input/Output Overview

Input:

• CDL Netlist (CDL:circuit definition language) is a SPICE-like format used to represent the schematic during LVS (layout-vs-schematic) using Mentor Graphics Calibre EDA tool
• Signal and device settings

Output:

• List of possible errors

  • Logic shorts
  • Possible leaks
  • Hi-Z inputs
  • Forward biased diodes
  • Mosfet gate vs source
  • Mosfet source vs drain
  • Electrical over-stress
  • LDD devices with incorrect source
  • Expected value check

Installation & Requirements

Requirements

• gcc 4.9.3+
• Python 2.7.14+
• Kivy 1.10+