Separate Utility submodule from HuanCun (OpenXiangShan#118)

* misc: import utils submodule * build.sc: add utils object * misc: rename submodule to Utility * misc: remove deprecated utils * misc: update utility * misc: adjust to new utility framework
cyyself · Dec 24, 2022 · 4c77bd6 · 4c77bd6
1 parent 4ff708e
commit 4c77bd6
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Showing 28 changed files with 35 additions and 1,360 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -2,3 +2,6 @@
 	path = rocket-chip
 	url = https://github.com/OpenXiangShan/rocket-chip.git
 	branch = 86a2f2cca699f149bcc082ef2828654a0a4e3f4b
+[submodule "Utility"]
+	path = Utility
+	url = https://github.com/OpenXiangShan/Utility
diff --git a/Utility b/Utility
diff --git a/build.sc b/build.sc
@@ -80,6 +80,16 @@ object rocketchip extends `rocket-chip`.common.CommonRocketChip {
 }
 
 
+object utility extends SbtModule with ScalafmtModule with CommonModule {
+
+  override def ivyDeps = Agg(common.getVersion("chisel3"))
+
+  override def millSourcePath = os.pwd / "Utility"
+
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
+}
+
+
 object HuanCun extends SbtModule with ScalafmtModule with CommonModule {
 
   override def millSourcePath = millOuterCtx.millSourcePath
@@ -90,7 +100,7 @@ object HuanCun extends SbtModule with ScalafmtModule with CommonModule {
     getVersion("chiseltest"),
   )
 
-  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip, utility)
 
   object test extends Tests {
     override def ivyDeps = super.ivyDeps() ++ Agg(

diff --git a/src/main/scala/huancun/BaseDirectory.scala b/src/main/scala/huancun/BaseDirectory.scala
@@ -24,8 +24,9 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.random.LFSR
 import freechips.rocketchip.tilelink.TLMessages
-import freechips.rocketchip.util.Pow2ClockDivider
+import freechips.rocketchip.util.{Pow2ClockDivider, ReplacementPolicy}
 import huancun.utils._
+import utility.{Code}
 
 trait BaseDirResult extends HuanCunBundle {
   val idOH = UInt(mshrsAll.W) // which mshr the result should be sent to

diff --git a/src/main/scala/huancun/DataStorage.scala b/src/main/scala/huancun/DataStorage.scala
@@ -22,7 +22,8 @@ package huancun
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
-import huancun.utils._
+import huancun.utils.{SRAMWrapper, XSPerfAccumulate}
+import utility._
 
 class DataStorage(implicit p: Parameters) extends HuanCunModule {
   val io = IO(new Bundle() {

diff --git a/src/main/scala/huancun/HuanCun.scala b/src/main/scala/huancun/HuanCun.scala
@@ -26,7 +26,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.{BundleField, BundleFieldBase, UIntToOH1}
 import huancun.prefetch._
-import huancun.utils.{FastArbiter, Pipeline, ResetGen}
+import utility._
 
 trait HasHuanCunParameters {
   val p: Parameters

diff --git a/src/main/scala/huancun/MSHRAlloc.scala b/src/main/scala/huancun/MSHRAlloc.scala
@@ -22,7 +22,8 @@ package huancun
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
-import utils._
+import huancun.utils._
+import utility.{ParallelOR, ParallelPriorityMux}
 import freechips.rocketchip.tilelink._
 
 class MSHRSelector(implicit p: Parameters) extends HuanCunModule {

diff --git a/src/main/scala/huancun/RequestBuffer.scala b/src/main/scala/huancun/RequestBuffer.scala
@@ -3,7 +3,8 @@ package huancun
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
-import huancun.utils.{FastArbiter, XSPerfAccumulate}
+import huancun.utils.XSPerfAccumulate
+import utility.FastArbiter
 
 class RequestBuffer(flow: Boolean = true, entries: Int = 16)(implicit p: Parameters) extends HuanCunModule {
 

diff --git a/src/main/scala/huancun/Slice.scala b/src/main/scala/huancun/Slice.scala
@@ -26,7 +26,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.leftOR
 import huancun.noninclusive.{MSHR, ProbeHelper, SliceCtrl}
 import huancun.prefetch._
-import huancun.utils.{FastArbiter, LatchFastArbiter, Pipeline}
+import utility._
 
 class Slice()(implicit p: Parameters) extends HuanCunModule {
   val io = IO(new Bundle {

diff --git a/src/main/scala/huancun/SourceB.scala b/src/main/scala/huancun/SourceB.scala
@@ -23,7 +23,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
-import huancun.utils.ParallelPriorityMux
+import utility.ParallelPriorityMux
 
 class SourceB(implicit p: Parameters) extends HuanCunModule {
   val io = IO(new Bundle() {

diff --git a/src/main/scala/huancun/SourceD.scala b/src/main/scala/huancun/SourceD.scala
@@ -24,7 +24,7 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages.{AcquireBlock, AcquirePerm, ReleaseAck}
-import huancun.utils._
+import utility._
 
 
 class SourceD(implicit p: Parameters) extends HuanCunModule {

diff --git a/src/main/scala/huancun/debug/TLLogger.scala b/src/main/scala/huancun/debug/TLLogger.scala
@@ -6,7 +6,7 @@ import chisel3.util._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.BundleMap
-import huancun.utils.ChiselDB
+import utility.ChiselDB
 
 trait HasCLikeTypes {
   // c++ firendly data types

diff --git a/src/main/scala/huancun/inclusive/Directory.scala b/src/main/scala/huancun/inclusive/Directory.scala
@@ -6,6 +6,7 @@ import chisel3.util._
 import freechips.rocketchip.util.SetAssocLRU
 import huancun._
 import huancun.utils._
+import utility.{ParallelMax, ParallelPriorityMux}
 
 // TODO: inclusive may have cache aliase too
 

diff --git a/src/main/scala/huancun/noninclusive/Directory.scala b/src/main/scala/huancun/noninclusive/Directory.scala
@@ -8,6 +8,7 @@ import huancun.MetaData._
 import huancun._
 import huancun.debug.{DirectoryLogger, TypeId}
 import huancun.utils._
+import utility.{ParallelMax, ParallelPriorityMux}
 
 trait HasClientInfo { this: HasHuanCunParameters =>
   // assume all clients have same params

diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala
@@ -9,6 +9,7 @@ import freechips.rocketchip.tilelink.TLHints._
 import huancun._
 import huancun.utils._
 import huancun.MetaData._
+import utility.ParallelMax
 
 class C_Status(implicit p: Parameters) extends HuanCunBundle {
   // When C nest A, A needs to know the status of C and tells C to release through to next level

diff --git a/src/main/scala/huancun/noninclusive/SliceCtrl.scala b/src/main/scala/huancun/noninclusive/SliceCtrl.scala
@@ -4,7 +4,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import huancun._
-import huancun.utils.RegNextN
+import utility.RegNextN
 
 class SliceCtrl()(implicit p: Parameters) extends HuanCunModule {
 

diff --git a/src/main/scala/huancun/prefetch/PrefetchReceiver.scala b/src/main/scala/huancun/prefetch/PrefetchReceiver.scala
@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
 import huancun._
-import huancun.utils.Pipeline
+import utility.Pipeline
 
 case class PrefetchReceiverParams(n: Int = 32) extends PrefetchParameters {
   override val hasPrefetchBit: Boolean = true

diff --git a/src/main/scala/huancun/prefetch/Prefetcher.scala b/src/main/scala/huancun/prefetch/Prefetcher.scala
@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
 import huancun._
-import huancun.utils.{Pipeline, RegNextN, ValidIODelay}
+import utility._
 
 class PrefetchReq(implicit p: Parameters) extends PrefetchBundle {
   val tag = UInt(fullTagBits.W)